參數(shù)資料
型號： IDT82V3280DQG8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 138/171頁
文件大?。?/td> 0K
描述： IC PLL WAN SE STRATUM 2 100-TQFP
標準包裝： 750
類型： 時鐘/頻率發(fā)生器，多路復用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，PECL
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 14:9
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP 裸露焊盤
供應商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
其它名稱： 82V3280DQG8
IDT82V3280
WAN PLL
Programming Information
69
December 9, 2008
INPUT_MODE_CNFG - Input Mode Configuration
Address: 09H
Type: Read / Write
Default Value: 10100XX0
Bit
Name
Description
7
AUTO_EXT_SYNC_EN Refer to the description of the EXT_SYNC_EN bit (b6, 09H).
6
EXT_SYNC_EN
This bit, together with the AUTO_EXT_SYNC_EN bit (b7, 09H), determines whether EX_SYNC1 is enabled to synchronize
the frame sync output signals.
5
PH_ALARM_TIMEOUT
This bit determines how to clear the phase lock alarm.
0: The phase lock alarm will be cleared when a ‘1’ is written to the corresponding INn_PH_LOCK_ALARM bit (b4/0,
43H~49H).
1: The phase lock alarm will be cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0]
(b7~6, 08H) in second
) which starts from when the alarm is raised. (default)
4 - 3
SYNC_FREQ[1:0]
These bits set the frequency of the frame sync signal input on the EX_SYNC1 pin.
00: 8 kHz (default)
01: 8 kHz.
10: 4 kHz.
11: 2 kHz.
2
IN_SONET_SDH
This bit selects the SDH or SONET network type.
0: SDH. The DPLL required clock is 2.048 MHz when the IN_FREQ[3:0] bits (b3~0, 14H~17H & 19H~22H) are ‘0001’; the
T0/T4 DPLL output from the 16E1/16T1 path is 16E1; and OUT9 outputs a 2.048 MHz signal if enabled.
1: SONET. The DPLL required clock is 1.544 MHz when the IN_FREQ[3:0] bits (b3~0, 14H~17H & 19H~22H) are ‘0001’; the
T0/T4 DPLL output from the 16E1/16T1 path is 16T1; and OUT9 outputs a 1.544 MHz signal if enabled.
The default value of this bit is determined by the SONET/SDH pin during reset.
1
MASTER_SLAVE
This bit is read only. It indicates the value of the MS/SL pin.
Its default value is determined by the MS/SL pin during reset.
0
REVERTIVE_MODE
This bit selects Revertive or Non-Revertive switch for T0 path.
0: Non-Revertive switch. (default)
1: Revertive switch.
76543210
AUTO_EXT_SY
NC_EN
EXT_SYNC_EN
PH_ALARM_TI
MEOUT
SYNC_FREQ1
SYNC_FREQ0
IN_SONET_SD
H
MASTER_SLAV
E
REVERTIVE_M
ODE
AUTO_EXT_SYNC_EN EXT_SYNC_EN
Synchronization
don’t-care
0
Disabled (default)
01
Enabled
1
Enabled if the T0 selected input clock is IN11; otherwise, disabled.
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