參數(shù)資料
型號: IDT82V3202NLG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 73/117頁
文件大?。?/td> 0K
描述: IC PLL WAN EBU SGL 68-VFQFPN
標準包裝: 21
類型: 時鐘/頻率發(fā)生器,多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 無/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤
供應商設備封裝: 68-VFQFPN(10x10)
包裝: 托盤
其它名稱: 82V3202NLG
IDT82V3202
EBU WAN PLL
Programming Information
59
September 11, 2009
INTERRUPTS2_STS - Interrupt Status 2
INTERRUPTS3_STS - Interrupt Status 3
Address: 0EH
Type: Read / Write
Default Value: 00XXXXXX
Bit
Name
Description
7
T0_OPERATING_MODE
This bit indicates the operating mode switch for T0 DPLL; i.e., whether the value in the
T0_DPLL_OPERATING_MODE[2:0] bits (b2~0, 52H) changes.
0: Has not switched. (default)
1: Has switched.
This bit is cleared by writing a ‘1’.
6
T0_MAIN_REF_FAILED
This bit indicates whether the T0 selected input clock has failed. The T0 selected input clock fails when its validity
changes from ‘valid’ to ‘invalid’; i.e., when there is a transition from ‘1’ to ‘0’ on the corresponding INn_CMOS bit (4AH).
0: Has not failed. (default)
1: Has failed.
This bit is cleared by writing a ‘1’.
5 - 0
-
Reserved.
Address: 0FH
Type: Read / Write
Default Value: 1XXXXXXX
Bit
Name
Description
7
EX_SYNC_ALARM
This bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from ‘0’ to ‘1’ on the
EX_SYNC_ALARM_MON bit (b7, 52H).
0: Has not occurred.
1: Has occurred. (default)
This bit is cleared by writing a ‘1’.
6 - 0
-
Reserved.
7
6
54321
0
T0_OPERATING
_MODE
T0_MAIN_REF_F
AILED
-----
-
7
6543210
EX_SYNC_ALARM
-
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