參數(shù)資料
型號： IDT82V3202NLG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 108/117頁
文件大?。?/td> 0K
描述： IC PLL WAN EBU SGL 68-VFQFPN
標準包裝： 21
類型： 時鐘/頻率發(fā)生器，多路復用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 無/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 68-VFQFN 裸露焊盤
供應商設備封裝： 68-VFQFPN（10x10）
包裝： 托盤
其它名稱： 82V3202NLG
IDT82V3202
EBU WAN PLL
Programming Information
90
September 11, 2009
6.2.8
OUTPUT CONFIGURATION REGISTERS
OUT2_FREQ_CNFG - Output Clock 2 Frequency Configuration
OUT1_FREQ_CNFG - Output Clock 1 Frequency Configuration
Address: 6DH
Type: Read / Write
Default Value: 00001000
Bit
Name
Description
7 - 4
OUT2_PATH_SEL[3:0]
These bits select an input to OUT2.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100 ~ 1111: Reserved.
3 - 0
OUT2_DIVIDER[3:0]
These bits select a division factor of the divider for OUT2.
The output frequency is determined by the division factor and the signal derived from T0 DPLL or T0/T4 APLL output
(selected by the OUT2_PATH_SEL[3:0] bits (b7~4, 6DH)). If the signal is derived from one of the T0 DPLL outputs, please
refer to Table 22 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
Table 23 for the division factor selection.
Address:71H
Type: Read / Write
Default Value: 00001000
Bit
Name
Description
7 - 4
OUT1_PATH_SEL[3:0]
These bits select an input to OUT1.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100 ~ 1111: Reserved.
3 - 0
OUT1_DIVIDER[3:0]
These bits select a division factor of the divider for OUT1.
The output frequency is determined by the division factor and the signal derived from T0 DPLL or T0/T4 APLL output
(selected by the OUT1_PATH_SEL[3:0] bits (b7~4, 71H)). If the signal is derived from one of the T0 DPLL outputs, please
refer to Table 22 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
Table 23 for the division factor selection.
76543210
OUT2_PATH_S
EL3
OUT2_PATH_S
EL2
OUT2_PATH_S
EL1
OUT2_PATH_S
EL0
OUT2_DIVIDER
3
OUT2_DIVIDER
2
OUT2_DIVIDER
1
OUT2_DIVIDER
0
76543210
OUT1_PATH_S
EL3
OUT1_PATH_S
EL2
OUT1_PATH_S
EL1
OUT1_PATH_S
EL0
OUT1_DIVIDER
3
OUT1_DIVIDER
2
OUT1_DIVIDER
1
OUT1_DIVIDER
0
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相關代理商/技術參數(shù)
參數(shù)描述
IDT82V3202NLG8 功能描述:IC PLL WAN EBU SGL 68-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3202NLGBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:EBU WAN PLL
IDT82V3255 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3255_08 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3255DK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
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