Table 29: Timing Definition for Standard Mode and Fast Mode
參數(shù)資料
型號： IDT82V3202NLG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 58/117頁
文件大?。?/td> 0K
描述： IC PLL WAN EBU SGL 68-VFQFPN
標準包裝： 21
類型： 時鐘/頻率發(fā)生器，多路復用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 無/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 68-VFQFN 裸露焊盤
供應商設備封裝： 68-VFQFPN（10x10）
包裝： 托盤
其它名稱： 82V3202NLG
IDT82V3202
EBU WAN PLL
I2C Programming Interface
45
September 11, 2009
Table 29: Timing Definition for Standard Mode and Fast Mode(1)
Symbol
Parameter
Standard Mode
Fast Mode
Unit
Min
Max
Min
Max
SCL
Serial clock frequency
0
100
0
400
KHz
tHD; STA
Hold time (repeated) START condition. After this period, the
first clock pulse is generated
4.0
-
0.5
-
s
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
s
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
-
s
tSU; STA
Set-up time for a repeated START condition
4.7
-
0.6
-
s
tHD; DAT
Data hold time: for CBUS compatible masters for I2C-bus
devices
5.0
0(2)
-
3.45(3)
-
0(2)
-
0.9(3)
s
tSU; DAT
Data set-up time
250
-
100(4)
-ns
tr
Rise time of both SDA and SCL signals
-
1000
20 + 0.1Cb(5)
300
ns
tf
Fall time of both SDA and SCL signals
-
300
20 + 0.1Cb(5)
300
ns
tSU; STO
Set-up time for STOP condition
4.0
-
0.6
-
s
tBUF
Bus free time between a STOP and START condition
4.7
-
1.3
-
s
Cb
Capacitive load for each bus line
-
400
-
400
pF
VnL
Noise margin at the LOW level for each connected device
(Including hysteresis)
0.1VDD
-
0.1VDD
-
V
VnH
Noise margin at the HIGH level for each connected device
(Including hysteresis)
0.2VDD
-
0.2VDD
-
V
tsp
Pulse width of spikes which must be suppressed by the input
filter
050
0
50
ns
Note:
1. All values referred to
VIHmin and VILmax levels (see Table 37)
2. A device must Internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the fall-
ing edge of SCL.
3. The maximum tHD; DAT has only to be met if the device does not strech the LOW period (tLOW) of the SCL signal.
4. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU; DAT ≥ 250 ns must then be met. This will automatically be
the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released.
5. Cb = total capacitance of one bus line in pF. If mixed with Hs-mode device, faster fall-times according to Table 39 allowed.
n/a = not applicable
相關PDF資料
PDF描述
IDT82V3255TFG IC PLL WAN SMC STRATUM 3 64-TQFP
IDT82V3280APFG IC PLL WAN SE STRATUM 2 100TQFP
IDT82V3285AEQG IC PLL WAN SE STRATUM 100TQFP
IDT82V3285EQG IC PLL WAN SE STRATUM 100TQFP
IDT82V3288BCG IC PLL WAN 3E STRATUM 2 208CABGA
相關代理商/技術參數(shù)
參數(shù)描述
IDT82V3202NLG8 功能描述:IC PLL WAN EBU SGL 68-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3202NLGBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:EBU WAN PLL
IDT82V3255 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3255_08 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3255DK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*