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參數(shù)資料
| 型號： | IDT82V3202NLG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 38/117頁 |
| 文件大小： | 0K |
| 描述： | IC PLL WAN EBU SGL 68-VFQFPN |
| 標準包裝： | 21 |
| 類型： | 時鐘/頻率發(fā)生器，多路復用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS |
| 輸出： | CMOS，LVDS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 68-VFQFPN（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | 82V3202NLG |
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IDT82V3202
EBU WAN PLL
Functional Description
27
September 11, 2009
3.8
SELECTED INPUT CLOCK SWITCH
If the input clock is selected by External Fast selection or by Forced
selection, it can be switched by setting the related registers (refer to
any time. In this case, whether the input clock is qualified for DPLL lock-
ing does not affect the clock switch.
When the input clock is selected by Automatic selection, the input
clock switch depends on its validity and priority. If the current selected
input clock is disqualified, a new qualified input clock may be switched
to.
3.8.1
INPUT CLOCK VALIDITY
For the input clocks, the validity depends on the results of input clock
quality monitoring (refer to Chapter 3.5 Input Clock Quality Monitoring).
When all of the following conditions are satisfied, the input clock is valid;
otherwise, it is invalid.
No no-activity alarm (the INn_CMOS_NO_ACTIVITY_ALARM
bit is ‘0’);
No frequency hard alarm (the INn_CMOS_FREQ_HARD_
ALARM bit is ‘0’);
If the IN_NOISE_WINDOW bit is ‘1’, all the edges of the input
clock of 2 kHz, 4 kHz or 8 kHz drift inside ±5%; if the
IN_NOISE_WINDOW bit is ‘0’, this condition is ignored.
No phase lock alarm, i.e., the INn_CMOS_PH_LOCK_ALARM
bit is ‘0’;
If the ULTR_FAST_SW bit is ‘1’, the T0 selected input clock
misses less than (<) 2 consecutive clock cycles; if the
ULTR_FAST_SW bit is ‘0’, this condition is ignored.
The validities of the input clocks are indicated by the INn_CMOS 1 bit
(n = 1 or 2). When the input clock validity changes (from ‘valid’ to ‘invalid’
or from ‘invalid’ to ‘valid’), the INn_CMOS 2 bit will be set. If the
INn_CMOS 3 bit is ‘1’, an interrupt will be generated.
When the T0 selected input clock has failed, i.e., the validity of the T0
selected input clock changes from ‘valid’ to ‘invalid’, the
T0_MAIN_REF_FAILED 1 bit will be set. If the T0_MAIN_REF_FAILED 2
bit is ‘1’, an interrupt will be generated. This interrupt can also be indi-
cated by hardware - the TDO pin, as determined by the
LOS_FLAG_TO_TDO bit. When the TDO pin is used to indicate this
interrupt, it will be set high when this interrupt is generated and will
remain high until this interrupt is cleared.
3.8.2
SELECTED INPUT CLOCK SWITCH
Revertive and Non-Revertive switches are supported, as selected by
the REVERTIVE_MODE bit.
The difference between Revertive and Non-Revertive switches is
that whether the selected input clock is switched when another qualified
input clock with a higher priority than the current selected input clock is
available for selection. In Non-Revertive switch, input clock switch is
minimized.
Conditions of the qualified input clocks available for T0 selection are
as the following:
Valid, i.e., the INn_CMOS 1 bit is ‘1’;
Priority enabled, i.e., the corresponding INn_CMOS_SEL
_PRIORITY[3:0] bits are not ‘0000’.
The input clock is disqualified if any of the above conditions is not
satisfied.
In summary, the selected input clock can be switched by:
External Fast selection;
Forced selection;
Revertive switch;
Non-Revertive switch.
3.8.2.1
Revertive Switch
In Revertive switch, the selected input clock is switched when
another qualified input clock with a higher priority than the current
selected input clock is available.
The selected input clock is switched if any of the following is satis-
fied:
The selected input clock is disqualified;
Another qualified input clock with a higher priority than the
selected input clock is available.
A qualified input clock with the higher priority is selected by revertive
switch. If more than one qualified input clock is available and has the
same priority, the input clock with the smaller ‘n’ is selected. See Table 8
for the ‘n’ assigned to each input clock.
3.8.2.2
Non-Revertive Switch
In Non-Revertive switch, the T0 selected input clock is not switched
when another qualified input clock with a higher priority than the current
selected input clock is available. In this case, the selected input clock is
switched and a qualified input clock with the higher priority is selected
only when the T0 selected input clock is disqualified. If more than one
qualified input clock is available and has the same priority, the input
clock with the smaller ‘n’ is selected. See Table 8 for the ‘n’ assigned to
each input clock.
3.8.3
SELECTED / QUALIFIED INPUT CLOCKS INDICATION
The
selected
input
clock
is
indicated
by
the
CURRENTLY_SELECTED_INPUT[3:0] bits.
The qualified input clocks with the two highest priorities are indicated
by
the
HIGHEST_PRIORITY_VALIDATED[3:0]
bits
and
the
SECOND_HIGHEST_PRIORITY_VALIDATED[3:0] bits respectively. If
more than one input clock has the same priority, the input clock with the
smaller ‘n’ is indicated by the HIGHEST_PRIORITY_VALIDATED[3:0]
bits. See Table 8 for the ‘n’ assigned to the input clock.
When the device is configured in Automatic selection and Revertive
switch
is
enabled,
the
input
clock
indicated
by
the
CURRENTLY_SELECTED_INPUT[3:0] bits is the same as the one indi-
cated by the HIGHEST_PRIORITY_VALIDATED[3:0] bits; otherwise,
they are not the same.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3202NLG8 | 功能描述:IC PLL WAN EBU SGL 68-VFQFPN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3202NLGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:EBU WAN PLL |
| IDT82V3255 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255_08 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3255DK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
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