參數(shù)資料
型號: IDT82P2521BH
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 83/147頁
文件大?。?/td> 0K
描述: IC LIU E1 21+1CH SHORT 640-PBGA
標準包裝: 5
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 640-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 640-PBGA-EP(31x31)
包裝: 托盤
其它名稱: 82P2521BH
IDT82P2521
21(+1) CHANNEL HIGH-DENSITY E1 LINE INTERFACE UNIT
Functional Description
40
December 7, 2005
3.2.7
TRANSMITTER POWER DOWN
Set the T_OFF bit (b5, TCF0,...) to ‘1’ will power down the corre-
sponding transmitter.
In this way, the corresponding transmit circuit is turned off. The pins
on the transmit line interface (including TTIPn and TRINGn) will be in
High-Z state. The input on the transmit system interface (including TDn,
TDPn, TDNn and TCLK) is ignored. The output on the transmit system
interface (i.e. TMFn) will be in High-Z state.
After clearing the T_OFF bit (b5, TCF0,...), it will take 1 ms for the
transmitter to achieve steady state, i.e., return to the previous configura-
tion and performance.
3.2.8
OUTPUT HIGH-Z ON TTIP AND TRING
TTIPn and TRINGn can be set to High-Z state globally or on a per-
channel basis.
The following three conditions will set TTIPn and TRINGn to High-Z
state globally:
Connecting the OE pin to low;
Loss of MCLK (i.e., no transition on MCLK for more than 1 ms);
Power on reset, hardware reset by pulling RST to low for more
than 2 s or global software reset by writing the RST register.
The following six conditions will set TTIPn and TRINGn to High-Z
state on a per-channel basis:
Writing ‘0’ to the OE bit (b6, TCF0,...);
Loss of TCLKn in Transmit Single Rail NRZ Format mode or
Transmit Dual Rail NRZ Format mode (i.e., no transition on TCLKn
for more than 64 XCLK1 cycles) except that the channel is in
Remote Loopback or transmit internal pattern with XCLK;
Transmitter power down;
Per-channel software reset by writing ‘1’ to the CHRST bit (b1,
Setting the THZ_OC bit (b4, TCF0,...) to ‘1’ when transmit driver
over-current is detected.
1. XCLK is derived from MCLK. It is 2.048 MHz .
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