T
參數(shù)資料
型號(hào)： IDT82P2521BH
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 77/147頁
文件大?。?/td> 0K
描述： IC LIU E1 21+1CH SHORT 640-PBGA
標(biāo)準(zhǔn)包裝： 5
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 640-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 640-PBGA-EP（31x31）
包裝： 托盤
其它名稱： 82P2521BH
IDT82P2521
21(+1) CHANNEL HIGH-DENSITY E1 LINE INTERFACE UNIT
Functional Description
35
December 7, 2005
3.2.2
TX CLOCK RECOVERY
The Tx Clock Recovery is used only when the transmit system inter-
face is in Dual Rail RZ Format mode. When the transmit system inter-
face is in other modes, the Tx Clock Recovery is bypassed
automatically.
The Tx Clock Recovery is used to recover the clock signal from the
data input on TDPn and TDNn.
3.2.3
ENCODER
The Encoder is used only when the transmit system interface is in
Single Rail NRZ Format mode. When the transmit system interface is in
other modes, the Encoder is bypassed automatically.
The data to be transmitted is encoded by AMI or HDB3 line code
rule. The line code rule is selected by the T_CODE bit (b2, TCF1,...).
3.2.4
WAVEFORM SHAPER
The IDT82P2521 provides two ways to manipulate the pulse shape
before data is transmitted:
Preset Waveform Template;
User-Programmable Arbitrary Waveform.
3.2.4.1 Preset Waveform Template
The waveform template meets G.703, as shown in Figure-15. It is
measured in the near end line side, as shown in Figure-16.
The PULS[3:0] should be set to ‘0000’ if differential signals (output
from TTIP and TRING) are coupled to a 75
coaxial cable using
Internal Impedance matching mode; the PULS[3:0] should be set to
‘0001’ for other E1 interfaces. Refer to Table-4 for details.
Figure-15 E1 Waveform Template
Figure-16 E1 Waveform Template Measurement Circuit
Table-3 Multiplex Pin Used in Transmit System Interface
Transmit System
Interface
Multiplex Pin Used On Transmit System
Interface
TDn / TDPn
TDNn / TMFn
TCLKn / TDNn
Single Rail NRZ Format
TDn 1
TMFn 2
TCLKn 3
Dual Rail NRZ Format
TDPn 1
TDNn 1
TCLKn 3
Dual Rail RZ Format
TDPn 1
TMFn 2
TDNn 1
Note:
1. The active level on TDn, TDPn and TDNn is selected by the TD_INV bit (b3,
2. TMFn is always active high.
3. The active edge of TCLKn is selected by the TCK_ES bit (b4, TCF1,...). If TCLKn is
missing, i.e., no transition for more than 64 E1 clock cycles, the TCKLOS_S bit (b3,
STAT0,...) will be set. A transition from ‘0’ to ‘1’ on the TCKLOS_S bit (b3, STAT0,...) or
any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the TCKLOS_S bit (b3, STAT0,...) will
set the TCKLOS_IS bit (b3, INTS0,...) to ‘1’, as selected by the TCKLOS_IES bit (b3,
INTES,...). When the TCKLOS_IS bit (b3, INTS0,...) is ‘1’, an interrupt will be reported
by INT if not masked by the TCKLOS_IM bit (b3, INTM0,...).
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
-0.20
0.00
0.20
0.40
0.60
0.80
1.00
1.20
Normalized
A
m
plitude
Time in Unit Intervals
IDT82P2821
VOUT
RLOAD
TTIPn
TRINGn
Note: RLOAD = 75
or 120 (+ 5%)
IDT82P2821
VOUT
RLOAD
TTIPn
TRINGn
Note: RLOAD = 75
or 120 (+ 5%)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT82P2521BHBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:21(1) Channel High-Density E1 Line Interface Unit
IDT82P2521BHG 功能描述:IC LIU E1 21+1CH SHORT 640-PBGA RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
IDT82P2521BHGBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:21(1) Channel High-Density E1 Line Interface Unit
IDT82P2808 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:8(+1) Channel High-Density T1/E1/J1 Line Interface Unit
IDT82P2808BB 功能描述:IC LIU T1/J1/E1 8+1CH 416-PBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
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