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參數(shù)資料
型號: IDT82P2521BH
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 16/147頁
文件大小: 0K
描述: IC LIU E1 21+1CH SHORT 640-PBGA
標(biāo)準(zhǔn)包裝: 5
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 640-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 640-PBGA-EP(31x31)
包裝: 托盤
其它名稱: 82P2521BH
IDT82P2521
21(+1) CHANNEL HIGH-DENSITY E1 LINE INTERFACE UNIT
Programming Information
112
December 7, 2005
INTS1 - Interrupt Status Register 1
Address: 021H, 061H, 0A1H, 0E1H, 121H, 161H, 1A1H, 1E1H, (CH1~CH8)
221H, 261H, 2A1H, 2E1H, 321H, 361H, 3A1H, 3E1H, (CH9~CH16)
421H, 461H, 4A1H, 4E1H, 521H, (CH17~CH21)
7E1H (CH0)
Type: Read / Write
Default Value: 00H
Bit
Name
Description
7
SAIS_IS
This bit indicates the interrupt status of the SAIS.
0: No SAIS interrupt is generated; or a ‘1’ is written to this bit. (default)
1: SAIS interrupt is generated and is reported by the INT pin. When the AIS_IES bit (b6, INTES,...) is ‘0’, a transition from ‘0’ to ‘1’
on the SAIS_S bit (b7, STAT1,...) set this bit to ‘1’; when the AIS_IES bit (b6, INTES,...) is ‘1’, any transition (from ‘0’ to ‘1’ or from
‘1’ to ‘0’) on the SAIS_S bit (b7, STAT1,...) set this bit to ‘1’.
6
LAIS_IS
This bit indicates the interrupt status of the LAIS.
0: No LAIS interrupt is generated; or a ‘1’ is written to this bit. (default)
1: LAIS interrupt is generated and is reported by the INT pin. When the AIS_IES bit (b6, INTES,...) is ‘0’, a transition from ‘0’ to ‘1’
on the LAIS_S bit (b6, STAT1,...) set this bit to ‘1’; when the AIS_IES bit (b6, INTES,...) is ‘1’, any transition (from ‘0’ to ‘1’ or from
‘1’ to ‘0’) on the LAIS_S bit (b6, STAT1,...) set this bit to ‘1’.
5
PA_IS
This bit indicates the interrupt status of the PRBS/ARB pattern synchronization.
0: No PRBS/ARB pattern synchronization interrupt is generated; or a ‘1’ is written to this bit. (default)
1: PRBS/ARB pattern synchronization interrupt is generated and is reported by the INT pin. When the PA_IES bit (b5, INTES,...)
is ‘0’, a transition from ‘0’ to ‘1’ on the PA_S bit (b5, STAT1,...) set this bit to ‘1’; when the PA_IES bit (b5, INTES,...) is ‘1’, any
transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the PA_S bit (b5, STAT1,...) set this bit to ‘1’.
4 - 2
-
Reserved.
1
IBA_IS
This bit indicates the interrupt status of the activate IB code.
0: No activate IB code interrupt is generated; or a ‘1’ is written to this bit. (default)
1: Activate IB code interrupt is generated and is reported by the INT pin. When the IB_IES bit (b0, INTES,...) is ‘0’, a transition
from ‘0’ to ‘1’ on the IBA_S bit (b1, STAT1,...) set this bit to ‘1’; when the IB_IES bit (b0, INTES,...) is ‘1’, any transition (from ‘0’ to
‘1’ or from ‘1’ to ‘0’) on the IBA_S bit (b1, STAT1,...) set this bit to ‘1’.
0
IBD_IS
This bit indicates the interrupt status of the deactivate IB code.
0: No deactivate IB code interrupt is generated; or a ‘1’ is written to this bit. (default)
1: Deactivate IB code interrupt is generated and is reported by the INT pin. When the IB_IES bit (b0, INTES,...) is ‘0’, a transition
from ‘0’ to ‘1’ on the IBD_S bit (b0, STAT1,...) set this bit to ‘1’; when the IB_IES bit (b0, INTES,...) is ‘1’, any transition (from ‘0’ to
‘1’ or from ‘1’ to ‘0’) on the IBD_S bit (b0, STAT1,...) set this bit to ‘1’.
7
6
5432
1
0
SAIS_IS
LAIS_IS
PA_IS
-
IBA_IS
IBD_IS
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