參數(shù)資料
型號(hào): IDT82P2521BH
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 64/147頁
文件大?。?/td> 0K
描述: IC LIU E1 21+1CH SHORT 640-PBGA
標(biāo)準(zhǔn)包裝: 5
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 640-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 640-PBGA-EP(31x31)
包裝: 托盤
其它名稱: 82P2521BH
IDT82P2521
21(+1) CHANNEL HIGH-DENSITY E1 LINE INTERFACE UNIT
Pin Description
23
December 7, 2005
REFB
Output
AJ18
REFB: Reference Clock Output B
REFB can output a recovered clock of one of the 22 channels, an external clock input on
CLKB or a free running clock. Refer to Section 3.5.2 Clock Outputs on REFA/REFB for
details.
The output on REFB can also be disabled, as determined by the REFB_EN bit (b6, REFB).
When the output is disabled, REFB is in High-Z state.
CLKA
Input
AH17
CLKA: External E1 Clock Input A
External E1 clock is input on this pin. The CKA_E1 bit (b5, REFA) should be set to match the
clock frequency.
When not used, this pin should be connected to GNDD.
CLKB
Input
AG17
CLKB: External E1 Clock Input B
External E1 clock is input on this pin. The CKB_E1 bit (b5, REFB) should be set to match the
clock frequency.
When not used, this pin should be connected to GNDD.
Common Control
VCOM[0]
VCOM[1]
Output
R4
P28
VCOM: Voltage Common Mode [1:0]
These pins are used only when the receive line interface is in Receive Differential mode and
connected without a transformer (transformer-less).
To enable these pins, the VCOMEN pin must be connected high. Refer to Figure-10 for the
connection.
When these pins are not used, they should be left open.
VCOMEN
Input
(Pull-Down)
AF26
VCOMEN: Voltage Common Mode Enable
This pin should be connected high only when the receive line interface is in Receive Differen-
tial mode and connected without a transformer (transformer-less).
When not used, this pin should be left open.
REF
-
D29
REF: Reference Resistor
An external resistor (10 K
, ±1%) is used to connect this pin to ground to provide a standard
reference current for internal circuit. This resistor is required to ensure correct device opera-
tion.
RIM
Input
(Pull-Down)
AH10
RIM: Receive Impedance Matching
In Receive Differential mode, when RIM is low, all 22 receivers become High-Z and only exter-
nal impedance matching is supported. In this case, the per-channel impedance matching con-
figuration bits - the R_TERM[2:0] bits (b2~0, RCF0,...) and the R120IN bit (b4, RCF0,...) - are
ignored.
In Receive Differential mode, when RIM is high, impedance matching is configured on a per-
channel basis by the R_TERM[2:0] bits (b2~0, RCF0,...) and the R120IN bit (b4, RCF0,...).
This pin can be used to control the receive impedance state for Hitless Protection applica-
In Receive Single Ended mode, this pin should be left open.
OE
Input
AJ10
OE: Output Enable
OE enables or disables all Line Drivers globally.
A high level on this pin enables all Line Drivers while a low level on this pin places all Line
Drivers in High-Z state and independent from related register settings.
Note that the functionality of the internal circuit is not affected by OE.
If this pin is not used, it should be tied to VDDIO.
This pin can be used to control the transmit impedance state for Hitless protection applica-
Name
I / O
Pin No.
Description
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