參數(shù)資料
型號(hào)： IDT72V51253L7.5BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： FIFO
英文描述： 128K X 18 OTHER FIFO, 4 ns, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁數(shù)： 50/50頁
文件大?。?/td> 460K
代理商： IDT72V51253L7.5BB
9
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
RDADD
Read Address Bus
LVTTL
on the RDADD bus will be selected on a rising edge of RCLK provided that RADEN is HIGH, (note, that
[5:0]
INPUT
data can be placed on to the Qout bus, read from the previously selected queue on this RCLK edge).
(Continued)
On the next rising RCLK edge after a read queue select, a data word from the previous queue will be
(RDADD5-P16
placed onto the outputs, Qout, regardless of the
REN input. Two RCLK rising edges after read queue
RDADD4-P15
select, data will be placed on to the Qout outputs from the newly selected queue, regardless of
RENdue
RDADD3-P14
to the first word fall through effect.
RDADD2-N14
The second function of the RDADD bus is to select the device of queues to be loaded on to the
PAEn
RDADD1-M16
bus during strobed flag mode. The most significant 3 bits, RDADD[5:3] are again used to select 1 of 8
RDADD0-M15)
possible multi-queue devices that may be connected in expansion mode. Address bits RDADD[2:0] are
don’t care during device selection. The device address present on the RDADD bus will be selected on the
rising edge of RCLK provided that ESTR is HIGH, (note, that data can be placed on to the Qout bus, read
fromthepreviouslyselectedqueueonthisRCLKedge).Pleasereferto Table2fordetailsonRDADDbus.
REN
Read Enable
LVTTL
The
REN input enables read operations from a selected queue based on a rising edge of RCLK. A
(T11)
INPUT
queue to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless
ofthestateof
REN.DatafromanewlyselectedqueuewillbeavailableontheQoutoutputbusonthesecond
RCLK cycle after queue selection regardless of
REN due to the FWFT operation. A read enable is not
required to cycle the
PAEn bus (in polled mode) or to select the device , (in direct mode).
SCLK
Serial Clock
LVTTL
If serial programming of the multi-queue device has been selected during master reset, the SCLK input
(N3)
INPUT
clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device
ontherisingedgeofSCLKprovidedthat
SENIisenabled,LOW.Whenexpansionofdevicesisperformed
the SCLK of all devices should be connected to the same source.
SENI
Serial Input Enable
LVTTL
During serial programming of a multi-queue device, data loaded onto the SI input will be clocked into the
(M2)
INPUT
part (via a rising edge of SCLK), provided the
SENI input of that device is LOW. If multiple devices are
cascaded,the
SENIinputshouldbeconnectedtotheSENOoutputofthepreviousdevice.Sowhenserial
loading of a given device is complete, its
SENO output goes LOW, allowing the next device in the chain
to be programmed (
SENOwillfollowSENIofagivendeviceoncethatdeviceisprogrammed).TheSENI
input of the master device (or single device), should be controlled by the user.
SENO
SerialOutput
LVTTL
This output is used to indicate that serial programming or default programming of the multi-queue device
(M1)
Enable
OUTPUT
has been completed.
SENOfollowsSENIonceprogrammingofadeviceiscomplete.Therefore,SENO
will go LOW after programming provided
SENIisLOW,onceSENIistakenHIGHagain,SENOwillalso
go HIGH. When the
SENOoutputgoesLOW,thedeviceisreadytobeginnormalread/writeoperations.
If multiple devices are cascaded and serial programming of the devices will be used, the
SENO output
should be connected to the
SENI input of the next device in the chain. When serial programming of the
first device is complete,
SENO will go LOW, thereby taking the SENI input of the next device LOW and
so on throughout the chain. When a given device in the chain is fully programmed the
SENO output
essentiallyfollowsthe
SENIinput.TheusershouldmonitortheSENOoutputofthefinaldeviceinthechain.
When this output goes LOW, serial loading of all devices has been completed.
SI
Serial In
LVTTL
Duringserialprogrammingthispinisloadedwiththeserialdatathatwillconfigurethemulti-queuedevices.
(L1)
INPUT
Data present on SI will be loaded on a rising edge of SCLK provided that
SENI is LOW. In expansion
modetheserialdatainputisloadedintothefirstdeviceinachain.Whenthatdeviceisloadedandits
SENO
hasgoneLOW,thedatapresentonSIwillbedirectlyoutputtotheSOoutput.TheSOpinofthefirstdevice
connects to the SI pin of the second and so on. The multi-queue device setup registers are shift registers.
SO
Serial Out
LVTTL
This output is used in expansion mode and allows serial data to be passed through devices in the chain
(M3)
OUTPUT
to complete programming of all devices. The SI of a device connects to SO of the previous device in the
chain. The SO of the final device in a chain should not be connected.
TCK(2)
JTAG Clock
LVTTL
Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test
(A8)
INPUT
operationsofthedevicearesynchronoustoTCK.DatafromTMSandTDIaresampledontherisingedge
of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs
to be tied to GND.
TDI(2)
JTAG Test Data
LVTTL
One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
(B9)
Input
INPUT
operation,testdata serially loaded via the TDI on the rising edge of TCK to either the Instruction Register,
ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
PIN DESCRIPTIONS (CONTINUED)
Symbol &
Name
I/O TYPE
Description
Pin No.
相關(guān)PDF資料
PDF描述
IDT742244CTL FAST CMOS OCTAL BUFFER/LINE DRIVERS
IDT742244CTLB FAST CMOS OCTAL BUFFER/LINE DRIVERS
IDT742244CTP FAST CMOS OCTAL BUFFER/LINE DRIVERS
IDT742244CTPB FAST CMOS OCTAL BUFFER/LINE DRIVERS
IDT742244CTPY FAST CMOS OCTAL BUFFER/LINE DRIVERS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72V51253L7-5BB8 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT72V51253L7-5BBI 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT72V51256L6BB 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT72V51256L6BB8 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT72V51256L7-5BB 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*