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| 型號： | IDT72V51253L7.5BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 128K X 18 OTHER FIFO, 4 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 17/50頁 |
| 文件大小： | 460K |
| 代理商： | IDT72V51253L7.5BB |
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24
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
PAFn FLAG BUS OPERATION
The IDT72V51233/72V51243/72V51253 multi-queue flow-control devices
can be configured for up to 4 queues, each queue having its own almost full
status.Anactivequeuehasitsflagstatusoutputtothediscreteflags,
FFandPAF,
on the write port. Queues that are not selected for a write operation can have
their
PAFstatusmonitoredviathePAFnbus.ThePAFnflagbusis4bitswide,
so that all 4 queues can have their status output to the bus. When a single
multi-queue device is used anywhere from 1 to 4 queues may be set-up within
thepart,eachqueuehavingitsowndedicated
PAFflagoutputonthePAFnbus.
Queues 1 through 4 have their
PAF status to PAF[0] through PAF[3]
respectively. If less than 4 queues are used then only the associated
PAFn
outputswillberequired,unused
PAFnoutputswillbedon’tcareoutputs.When
devices are connected in expansion mode the
PAFn flag bus can also be
expanded beyond 4 bits to produce a wider
PAFn bus that encompasses all
queues.
Alternatively,the4bit
PAFnflagbusofeachdevicecanbeconnectedtogether
to form a single 4 bit bus, i.e.
PAF[0]ofdevice1willconnecttoPAF[0]ofdevice
2 etc. When connecting devices in this manner the
PAFn can only be driven
by a single device at any time, (the
PAFn outputs of all other devices must be
in high impedance state). There are two methods by which the user can select
which device has control of the bus, these are “Direct” (Addressed) mode or
“Polled” (Looped) mode, determined by the state of the FM (flag Mode) input
during a Master Reset.
PAFn BUS EXPANSION - DIRECT MODE
If FM is LOW at Master Reset then the
PAFn bus operates in Direct
(addressed)mode.Indirectmodetheusercanaddressthedevicetheyrequire
to control the
PAFn bus. The address present on the 3 most significant bits of
the WRADD[4:0] address bus with FSTR (
PAF flag strobe), HIGH will be
selected as the device on a rising edge of WCLK. So to address the first device
in a bank of devices the WRADD[4:0] address should be “000xx” the second
device“001xx”andsoon.The3mostsignificantbitsoftheWRADD[4:0]address
buscorrespondtothedeviceIDinputsID[2:0].The
PAFnbuswillchangestatus
toshowthenewdeviceselected1WCLKcycleafterdeviceselection.Note,that
if a read or write operation is occurring to a specific queue, say queue ‘x’ on
the same cycle as a
PAFn bus switch to the device containing queue ‘x’, then
there may be an extra WCLK cycle delay before that queues status is correctly
shown on the respective output of the
PAFn bus. However, the “active” PAF
flag will show correct status at all times.
Devices can be selected on consecutive WCLK cycles, that is the device
controlling the
PAFn bus can change every WCLK cycle. Also, data present
ontheinputbus,Din,canbewrittenintoaqueueonthesameWLCKrisingedge
that a device is being selected on the
PAFnbus,theonlyrestrictionbeingthat
a write queue selection and
PAFnbusselectioncannotbemadeonthesame
cycle.
PAFn BUS EXPANSION– POLLED MODE
IfFMisHIGHatMasterResetthenthe
PAFnbusoperatesinPolled(Looped)
mode. In polled mode the
PAFnbusautomaticallycyclesthroughthedevices
connected in expansion. In expansion mode one device will be set as the
Master,MASTinputtiedHIGH,allotherdeviceswillhaveMASTtiedLOW.The
master device is the first device to take control of the
PAFn bus and place the
PAFstatusofitsqueuesontothebusonthefirstrisingedgeofWCLKafterthe
MRSinputgoesHIGHonceaMasterResetiscomplete.TheFSYNC(PAFsync
pulse) output of the first device (master device), will be HIGH for one cycle of
WCLK indicating that it is has control of the
PAFn bus for that cycle.
The device also passes a “token” onto the next device in the chain, the next
device assuming control of the
PAFnbusonthenextWCLKcycle.Thistoken
passing is done via the FXO outputs and FXI inputs of the devices (“
PAFn
Expansion Out” and “
PAFnExpansionIn”).TheFXOoutputofthefirstdevice
connecting to the FXI input of the second device in the chain, the FXO of the
second device connects to the FXI of the third device and so on. The FXO of
thefinaldeviceinachainconnectstotheFXIofthefirstdevice,sothatoncethe
PAFn bus has cycled through all devices control is again passed to the first
device.TheFXOoutputofadevicewillbeHIGHfortheWCLKcycleithascontrol
of the bus.
Please refer to Figure 24,
PAFn Bus – Polled Mode for timing information.
PAEn FLAG BUS OPERATION
The IDT72V51233/72V51243/72V51253 multi-queue flow-control devices
can be configured for up to 4 queues, each queue having its own almost empty
status.Anactivequeuehasitsflagstatusoutputtothediscreteflags,
OVandPAE,
on the read port. Queues that are not selected for a read operation can have
their
PAEstatusmonitoredviathePAEnbus.ThePAEnflagbusis4bitswide,
so that all 4 queues can have their status output to the bus.
Whenasinglemulti-queuedeviceisusedanywherefrom1to4queuesmay
beset-upwithinthepart,eachqueuehavingitsowndedicated
PAEnflagoutput
on the
PAEnbus.Queues1through4havetheirPAEstatustoPAE[0]through
PAE[3] respectively. If less than 4 queues are used then only the associated
PAEnoutputswillberequired,unusedPAEnoutputswillbedon’tcareoutputs.
When devices are connected in expansion mode the
PAEn flag bus can also
be expanded beyond 4 bits to produce a wider
PAEn bus that encompasses
all queues.
Alternatively,the4bit
PAEnflagbusofeachdevicecanbeconnectedtogether
to form a single 4 bit bus, i.e.
PAE[0]ofdevice1willconnecttoPAE[0]ofdevice
2etc.Whenconnectingdevicesinthismannerthe
PAEnbuscanonlybedriven
by a single device at any time, (the
PAEn outputs of all other devices must be
in high impedance state). There are two methods by which the user can select
which device has control of the bus, these are “Direct” (Addressed) mode or
“Polled” (Looped) mode, determined by the state of the FM (flag Mode) input
during a Master Reset.
PAEn BUS EXPANSION- DIRECT MODE
If FM is LOW at Master Reset then the
PAEn bus operates in Direct
(addressed)mode.Indirectmodetheusercanaddressthedevicetheyrequire
to control the
PAEn bus. The address present on the 3 most significant bits of
the RDADD[5:0] address bus with ESTR (
PAE flag strobe), HIGH will be
selected as the device on a rising edge of RCLK. So to address the first device
in a bank of devices the RDADD[5:0] address should be “000xx” the second
device“001xx”andsoon.The3mostsignificantbitsoftheRDADD[5:0]address
buscorrespondtothedeviceIDinputsID[2:0].The
PAEnbuswillchangestatus
toshowthenewdeviceselected1RCLKcycleafterdeviceselection.Note,that
if a read or write operation is occurring to a specific queue, say queue ‘x’ on
the same cycle as a
PAEn bus switch to the device containing queue ‘x’, then
there may be an extra RCLK cycle delay before that queues status is correctly
shown on the respective output of the
PAEn bus. However, the “active” PAE
flag will show correct status at all times.
Devices can be selected on consecutive RCLK cycles, that is the device
controllingthe
PAEnbuscanchangeeveryRCLKcycle.Also,datacanberead
out of a queue on the same RCLK rising edge that a device is being selected
onthe
PAEnbus,theonlyrestrictionbeingthatareadqueueselectionandPAEn
bus selection cannot be made on the same cycle.
PAEn BUS EXPANSION- POLLED MODE
If FM is HIGH at Master Reset then the
PAEn bus operates in Polled
(Looped) mode. In polled mode the
PAEn bus automatically cycles through
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| IDT72V51253L7-5BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51253L7-5BBI | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51256L6BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51256L6BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51256L7-5BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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