參數(shù)資料
型號: IDT72V51253L7.5BB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: FIFO
英文描述: 128K X 18 OTHER FIFO, 4 ns, PBGA256
封裝: 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁數(shù): 18/50頁
文件大?。?/td> 460K
代理商: IDT72V51253L7.5BB
25
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
the devices connected in expansion. In expansion mode one device will be
set as the Master, MAST input tied HIGH, all other devices will have MAST
tied LOW. The master device is the first device to take control of the
PAEnbus
and place the
PAE status of its queues onto the bus on the first rising edge of
RCLK after the
MRS input goes HIGH once a Master Reset is complete. The
ESYNC(
PAEsyncpulse)outputofthefirstdevice(masterdevice),willbeHIGH
for one cycle of RCLK indicating that it is has control of the
PAEn bus for that
cycle.
The device also passes a “token” onto the next device in the chain, the next
device assuming control of the
PAEnbusonthenextRCLKcycle.Thistoken
passing is done via the EXO outputs and EXI inputs of the devices (“
PAEn
Expansion Out” and “
PAEnExpansionIn”).TheEXOoutputofthefirstdevice
connecting to the EXI input of the second device in the chain, the EXO of the
second device connects to the EXI of the third device and so on. The EXO of
thefinaldeviceinachainconnectstotheEXIofthefirstdevice,sothatoncethe
PAEn bus has cycled through all devices control is again passed to the first
device.TheEXOoutputofadevicewillbeHIGHfortheRCLKcycleithascontrol
of the bus.
Please refer to Figure 25,
PAEn Bus – Polled Mode for timing information.
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