參數(shù)資料
型號: IDT72V51253L7.5BB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: FIFO
英文描述: 128K X 18 OTHER FIFO, 4 ns, PBGA256
封裝: 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁數(shù): 14/50頁
文件大小: 460K
代理商: IDT72V51253L7.5BB
21
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
within a queue can be at any point within that queues depth. This location can
be user programmed via the serial port or one of the default values (8 or 128)
can be selected if the user has performed default programming.
As mentioned, every queue within a multi-queue device has its own almost
empty status, when a queue is selected on the read port, this status is output
via the
PAE flag. The PAE flag value for each queue is programmed during
multi-queue device programming (along with the number of queues, queue
depthsandalmostfullvalues).The
PAEoffsetvalue,n,forarespectivequeue
can be programmed to be anywhere between ‘0’ and ‘D’, where ‘D’ is the total
memory depth for that queue. The
PAE value of different queues within the
same device can be different values.
Whenqueueswitchesarebeingmadeonthereadport,the
PAEflagoutput
will switch to the new queue and provide the user with the new queue status,
on the second cycle after a new queue selection is made, on the same RCLK
cyclethatdataactuallyfallsthroughtotheoutputregisterfromthenewqueue.
That is, a new queue can be selected on the read port via the RDADD bus,
RADENenableandarisingedgeofRCLK.OnthesecondrisingedgeofRCLK
followingaqueueselection,thedatawordfromthenewqueuewillbeavailable
at the output register and the
PAEflagoutputwillshowtheemptystatusofthe
newly selected queue. The
PAE is flag output is double register buffered, so
when a read operation occurs at the almost empty boundary causing the
selected queue status to go almost empty the
PAEwillgoLOW2RCLKcycles
after the read. The same is true when a write occurs, there will be a 2 RCLK
cycle delay after the write operation.
So the
PAE flag delays are:
from a read operation to
PAE flag LOW is 2 RCLK + tRAE
The delay from a write operation to
PAEflagHIGHistSKEW2+RCLK+tRAE
Note, if tSKEW is violated there will be one added RCLK cycle delay.
The
PAEflagissynchronoustotheRCLKandalltransitionsofthePAEflag
occur based on a rising edge of RCLK. Internally the multi-queue device
monitorsandkeepsarecordofthealmostemptystatusforallqueues.Itispossible
that the status of a
PAEflagmaybechanginginternallyeventhoughthatflagis
not the active queue flag (selected on the read port). A queue selected on the
writeportmayexperienceachangeofitsinternalalmostemptyflagstatusbased
on write operations. The multi-queue flow-control device also provides a
duplicateofthe
PAEflagonthePAE[3:0]flagbus,thiswillbediscussedindetail
in a later section of the data sheet.
See Figures 20 and 21 for Almost Empty flag timing and queue switching.
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