參數(shù)資料
型號(hào)： IDT72V51253L7.5BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： FIFO
英文描述： 128K X 18 OTHER FIFO, 4 ns, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁(yè)數(shù)： 16/50頁(yè)
文件大小： 460K
代理商： IDT72V51253L7.5BB
23
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED)
NOTE:
n = Almost Empty Offset value.
Default values: if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAEn Timing
Assertion:
Read Operation to
PAEn LOW: 2 RCLK* + tPAE
De-assertion: Write to
PAEn HIGH: tSKEW3 + RCLK* + tPAE
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 RCLK* + tPAE
* If a queue switch is occurring on the read port at the point of flag assertion or de-assertion
there may be one additional RCLK clock cycle delay.
Programmable Almost Empty Flag Bus,
PAEn Boundary
I/O Set-Up
PAEn Boundary Condition
In18 to out18 or In9 to out9
PAEn Goes HIGH after
(Both ports selected for same queue when the 1st
n+2 Writes
Word is written in until the boundary is reached)
(see note below for timing)
In18 to out18 or In9 to out9
PAEn Goes HIGH after
(Write port only selected for same queue when the n+1 Writes
1st Word is written in until the boundary is reached) (see note below for timing)
In18 to out9
PAEn Goes HIGH after n+1
Writes (see below for timing)
In9 to out18
PAEn Goes HIGH after
(Both ports selected for same queue when the 1st
([n+2] x 2) Writes
Word is written in until the boundary is reached)
(see note below for timing)
In9 to out18
PAEn Goes HIGH after
(Write port only selected for same queue when the ([n+1] x 2) Writes
1st Word is written in until the boundary is reached) (see note below for timing)
Programmable Almost Full Flag,
PAF & PAFn Bus Boundary
I/O Set-Up
PAF & PAFn Boundary
In18 to out18 or In9 to out9
PAF/PAFn Goes LOW after
(Both ports selected for same queue when the 1st
D+1-m Writes
Word is written in until the boundary is reached)
(see note below for timing)
In18 to out18 or In9 to out9
PAF/PAFn Goes LOW after
(Write port only selected for same queue when the D-m Writes
1st Word is written in until the boundary is reached) (see note below for timing)
In18 to out9
PAF/PAFn Goes LOW after
D-mWrites(seebelowfortiming)
In9 to out18
PAF/PAFn Goes LOW after
([D+1-m] x 2) Writes
(see note below for timing)
NOTE:
D = Queue Depth
m = Almost Full Offset value.
Default values:
if DF is LOW at Master Reset then m = 8
if DF is HIGH at Master Reset then m= 128
PAF Timing
Assertion:
Write Operation to
PAF LOW: 2 WCLK + tWAF
De-assertion: Read to
PAF HIGH: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 WCLK + tWAF
PAFn Timing
Assertion:
Write Operation to
PAFn LOW: 2 WCLK* + tPAF
De-assertion: Read to
PAFn HIGH: tSKEW3 + WCLK* + tPAF
If tSKEW3 is violated there may be 1 added clock: tSKEW3 + 2 WCLK* + tPAF
* If a queue switch is occurring on the write port at the point of flag assertion or de-assertion
there may be one additional WCLK clock cycle delay.
NOTE:
n = Almost Empty Offset value.
Default values:
if DF is LOW at Master Reset then n = 8
if DF is HIGH at Master Reset then n = 128
PAE Timing
Assertion:
Read Operation to
PAE LOW: 2 RCLK + tRAE
De-assertion: Write to
PAE HIGH: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there may be 1 added clock: tSKEW2 + 2 RCLK + tRAE
Programmable Almost Empty Flag,
PAE Boundary
I/O Set-Up
PAE Assertion
In18 to out18 or In9 to out9
PAE Goes HIGH after n+2
(Both ports selected for same queue when the 1st
Writes
Word is written in until the boundary is reached)
(see note below for timing)
In18 to out9
PAE Goes HIGH after n+1
(Both ports selected for same queue when the 1st
Writes
Word is written in until the boundary is reached)
(see note below for timing)
In9 to out18
PAE Goes HIGH after
(Both ports selected for same queue when the 1st
([n+2] x 2) Writes
Word is written in until the boundary is reached)
(see note below for timing)
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