參數(shù)資料
型號(hào)： IDT72V51253L7.5BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： FIFO
英文描述： 128K X 18 OTHER FIFO, 4 ns, PBGA256
封裝： 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256
文件頁數(shù)： 27/50頁
文件大?。?/td> 460K
代理商： IDT72V51253L7.5BB
33
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WCLK
WADEN
tQH
tQS
tAH
tAS
WRADD
D
1
Q
3
FF (D
evice
1)
tFFLZ
5941
drw13
WEN
tENS
tAH
tAS
tAH
tAS
tQH
tQS
D
2
Q
2
tQH
tQS
tDH
tDS
W
D
1
Q3
tDH
tDS
Din
tWFF
HIGH-Z
RCLK
1
2
tENH
tENS
tENH
Addr=00111
D
1
Q
0
tWFF
W
D
1
Q0
tFFHZ
tWFF
HIGH-Z
FF (D
evice
2)
tFFHZ
HIGH-Z
tFFLZ
tSKEW1
Addr=00100
tAH
tAS
RDADD
D
1
Q
0
tQH
tQS
RADEN
*A*
*B*
*C*
*D*
*E*
*F*
*G*
*H*
*I*
No
Write
*J*
Qout
tA
Previous
Q
W
X-1
Previous
Q
W
X
PFT
D
1
-Q
0
Word
W
0
PFT
*AA*
*BB*
*CC*
Addr=01010
Addr=001000
Figure
11.
Full
Flag
Timing
in
Expansion
Mode
NOTE:
1.
REN
=
HIGH.
Cycle
:
*A*
Queue,
Q3
of
device
1
is
selected
on
the
write
port.
The
FF
flag
of
device
1
is
in
High-Impedance,
the
write
port
of
device
2
was
previously
selected.
WEN
is
HIGH
so
no
write
occurs.
*AA*
Queue,
Q0
of
device
1
is
selected
on
the
read
port.
*B*
The
FF
flag
of
device
2
goes
to
High-Impedance
and
the
FF
flag
of
device
1
goes
to
Low-Impedance,
logic
HIGH
indicating
that
D1
Q3
is
not
full.
WEN
is
HIGH
so
no
write
occurs.
*BB*
Word,
Wx
is
read
from
the
previously
selected
queue,
(due
to
FWFT).
*C*
Word,
Wd
is
written
into
Q3
of
D1.
This
write
operation
causes
Q3
to
go
full,
FF
goes
LOW.
*CC*
The
first
word
from
Q0
of
D1
selected
on
cycle
*AA*
is
read
out,
this
occurred
regardless
of
REN
due
to
FWFT.
This
read
caused
Q0
to
go
not
full,
therefore
the
FF
flag
will
go
HIGH
after:
t
SKEW1
+
t
WFF
.
Note
if
t
SKEW1
is
violated
the
time
to
FF
flag
HIGH
is
t
SKEW1
+
WLCK
+
t
WFF
.
*D*
Queue,
Q0
of
device
1
is
selected
on
the
write
port.
No
write
occurs
on
this
cycle.
*E*
The
FF
flag
updates
to
show
the
status
of
D1
Q0,
it
is
not
full,
FF
goes
HIGH.
*F*
Word,
Wd
is
written
into
Q0
of
D1.
This
causes
the
queue
to
go
full,
FF
goes
LOW.
*G*
No
write
occurs
regardless
of
WEN
,the
FF
flag
is
LOW
preventing
writes.
*H*
The
FF
flag
goes
HIGH
due
to
the
read
from
Q0
of
D1
on
cycle
*CC*.
(This
read
is
not
an
enabled
read,
it
is
due
to
the
FWFT
operation
).
*I*
Queue,
Q2
of
device
2
is
selected
on
the
write
port.
*J*
The
FF
flag
of
device
1
goes
to
High-Impedance,
this
device
was
deselected
on
the
write
port
on
cycle
*I*.
The
FF
flag
of
device
2
goes
to
Low-Impedance
and
provides
status
of
Q2
of
D2.
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