- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299201 > IDT72V51253L7.5BB (INTEGRATED DEVICE TECHNOLOGY INC) 128K X 18 OTHER FIFO, 4 ns, PBGA256 PDF資料下載
參數(shù)資料
| 型號： | IDT72V51253L7.5BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | FIFO |
| 英文描述： | 128K X 18 OTHER FIFO, 4 ns, PBGA256 |
| 封裝： | 17 X 17 MM, 1 MM PITCH, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 32/50頁 |
| 文件大?。?/td> | 460K |
| 代理商： | IDT72V51253L7.5BB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁當(dāng)前第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁
38
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72V51233/72V51243/72V51253 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(4 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
WCLK
WADEN
tQH
tQS
tAH
tAS
WRADD
D1 Q2
PAF
(Device 1)
tAFLZ
5941 drw20
WEN
tENS
tAH
tAS
tQH
tQS
tDH
tDS
WD-m
Din
tWAF
HIGH-Z
tENH
D1 Q0
PAF
(Device 2)
tFFHZ
12
D1 Q2
*B*
*C*
*E*
*F*
*D*
*A*
Figure 18. Almost Full Flag Timing and Queue Switch
Figure 19. Almost Full Flag Timing
WCLK
WEN
PAF
RCLK
tWAF
REN
5941 drw21
D - (m+1) words in Queue
D - m words in Queue
1
2
1
D-(m+1) words
in Queue
tWAF
tENH
tENS
tSKEW2
tENH
tENS
tCLKL
Cycle:
*A* Queue 2 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The
PAF output of device 1 is High-Impedance.
*B* No write occurs.
*C* Word, Wd-m is written into Q2 causing the
PAF flag to go from HIGH to LOW. The flag latency is 2 WCLK cycles + tWAF.
*D* Queue 0 if device 1 is now selected for write operations. This queue is not almost full, therefore the
PAF flag will update after a 2 WCLK + tWAF latency.
*E* The
PAF flag goes LOW based on the write 2 cycles earlier.
*F* The
PAF flag goes HIGH due to the queue switch to Q0.
NOTE:
1. The waveform here shows the
PAF flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost full boundary.
Flag Latencies:
Assertion: 2*WCLK + tWAF
De-assertion: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there will be one extra WCLK cycle.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT742244CTL | FAST CMOS OCTAL BUFFER/LINE DRIVERS |
| IDT742244CTLB | FAST CMOS OCTAL BUFFER/LINE DRIVERS |
| IDT742244CTP | FAST CMOS OCTAL BUFFER/LINE DRIVERS |
| IDT742244CTPB | FAST CMOS OCTAL BUFFER/LINE DRIVERS |
| IDT742244CTPY | FAST CMOS OCTAL BUFFER/LINE DRIVERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72V51253L7-5BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51253L7-5BBI | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51256L6BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51256L6BB8 | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
| IDT72V51256L7-5BB | 功能描述:IC FLOW CTRL MULTI QUEUE 256-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。