參數(shù)資料
型號: ICS8430S10BYI-02LFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 9/31頁
文件大?。?/td> 0K
描述: IC CLK GENERATOR PLL 48TQFP
標準包裝: 1,000
類型: 時鐘/頻率發(fā)生器,扇出緩沖器(分配),多路復用器
PLL:
主要目的: Cavium 處理器
輸入: LVCMOS,LVDS,LVPECL,LVTTL,SSTL,晶體
輸出: LVCMOS,LVDS,LVPECL,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 2:10
差分 - 輸入:輸出: 是/是
頻率 - 最大: 133.33MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤
供應商設(shè)備封裝: 48-PTQFP-EP(7x7)
包裝: 帶卷 (TR)
ICS8430S10BYI-02 REVISION C JANUARY 17, 2011
17
2011 Integrated Device Technology, Inc.
ICS8430S10I-02 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, SSTL, and other differential
signals. Both VSWING and VOH must meet the VPP and VCMR input
requirements. Figures 2A to 2D show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. If the driver is from another vendor, use their
termination recommendation.
Figure 2A. CLK/nCLK Input
Driven by a 3.3V LVDS Driver
Figure 2C. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2B. CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input
Driven by a 2.5V SSTL Driver
3.3V
R1
100
LVDS
CLK
nCLK
3.3V
Receiver
Zo = 50
Zo = 50
R3
125
R4
125
R1
84
R2
84
3.3V
Zo = 50
Zo = 50
CLK
nCLK
3.3V
LVPECL
Differential
Input
CLK
nCLK
Differential
Input
LVPECL
3.3V
Zo = 50
Zo = 50
3.3V
R1
50
R2
50
R2
50
CLK
nCLK
Differential
Input
SSTL
2.5V
Zo = 60
Zo = 60
2.5V
3.3V
R1
120
R2
120
R3
120
R4
120
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