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參數(shù)資料
| 型號： | ICS8430S10BYI-02LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 23/31頁 |
| 文件大小： | 0K |
| 描述： | IC CLK GENERATOR PLL 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時鐘/頻率發(fā)生器，扇出緩沖器（分配），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | Cavium 處理器 |
| 輸入： | LVCMOS，LVDS，LVPECL，LVTTL，SSTL，晶體 |
| 輸出： | LVCMOS，LVDS，LVPECL，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 133.33MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-PTQFP-EP（7x7） |
| 包裝： | 帶卷 (TR) |
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ICS8430S10BYI-02 REVISION C JANUARY 17, 2011
3
2011 Integrated Device Technology, Inc.
ICS8430S10I-02 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 13, 23
VDD
Power
Core supply pins.
2
nOE_D
Input
Pulldown
Active LOW output enable for Bank D outputs. When logic HIGH, the outputs are
in high impedance (HI-Z). When logic LOW, the outputs are enabled.
LVCMOS/LVTTL interface levels.
3, 12, 30, 31,
39, 42, 46
GND
Power
Power supply ground.
4
nPLL_SEL
Input
Pulldown
PLL bypass. When LOW, PLL is enable. When HIGH, PLL is bypassed.
LVCMOS/LVTTL interface levels.
5,
6
XTAL_IN,
XTAL_OUT
Input
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
7
nXTAL_SEL
Input
Pulldown
Selects XTAL inputs when LOW. Selects differential clock (CLK, nCLK) input when
HIGH. LVCMOS/LVTTL interface levels.
8
CLK
Input
Pulldown
Non-inverting differential clock input.
9
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. Internal resistor bias to VDD/2.
10
nOE_C
Input
Pulldown
Active LOW output enable for Bank C output. When logic HIGH, the output is in
high impedance (HI-Z). When logic LOW, QC output is enabled. LVCMOS/LVTTL
interface levels.
11
nOE_B
Input
Pulldown
Active LOW output enable for Bank B outputs. When logic HIGH, the outputs are in
high impedance (HI-Z). When logic LOW, the outputs are enabled.
LVCMOS/LVTTL interface levels.
14
nOE_A
Input
Pulldown
Active LOW output enable for Bank A outputs. LVCMOS/LVTTL interface levels.
15,
16
SPI_SEL1,
SPI_SEL0
Input
Pulldown
Selects the SPI PLL clock reference frequency. See Table 3D.
17,
18
PCI_SEL1,
PCI_SEL0
Input
Pulldown
Selects the PCI, PCI-X reference clock output frequency. See Table 3C.
LVCMOS/LVTTL interface levels.
19,
20
DDR_SEL1,
DDR_SEL0
Input
Pulldown
Selects the DDR reference clock output frequency. See Table 3B.
LVCMOS/LVTTL interface levels.
21, 22
nQA, QA
Output
Differential output pair. Selectable between LVPECL and LVDS interface levels.
24
VDDA
Power
Analog supply pin.
25, 28
VDDO_B
Power
Bank B output supply pins. 3.3 V or 2.5V supply.
26, 27
QB1, QB0
Output
Single-ended Bank B outputs. LVCMOS/LVTTL interface levels.
29
nOE_REF
Input
Pulldown
Active LOW output enable. When logic HIGH, the QREF[2:0] outputs are in high
impedance (HI-Z). When logic LOW, the QREF[2:0] outputs are enabled.
LVCMOS/ LVTTL interface levels.
32
CORE_SEL
Input
Pulldown
Selects the processor core clock output frequency. The output frequency is 50MHz
when LOW, and 33.333MHz when HIGH. See Table 3A. LVCMOS/LVTTL
interface levels.
33, 34
QD1, QD0
Output
Single-end Bank D outputs. LVCMOS/LVTTL interface levels.
35
QC
Output
Single-end Bank C output. LVCMOS/LVTTL interface levels.
36
VDDO_CD
Power
Bank C and Bank D output supply pin. 3.3 V or 2.5V supply.
Pin descriptions continue on the next page.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS8430S10I-03 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Clock Generator for Cavium Processors |
| ICS8431-01 | 制造商:ICS 制造商全稱:ICS 功能描述:200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER |
| ICS843101-312 | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101AG-312 | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101AG-312LF | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
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