參數(shù)資料
型號(hào)： ICS8430S10BYI-02LFT
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 1/31頁
文件大小： 0K
描述： IC CLK GENERATOR PLL 48TQFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 時(shí)鐘/頻率發(fā)生器，扇出緩沖器（分配），多路復(fù)用器
PLL： 是
主要目的： Cavium 處理器
輸入： LVCMOS，LVDS，LVPECL，LVTTL，SSTL，晶體
輸出： LVCMOS，LVDS，LVPECL，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:10
差分 - 輸入:輸出： 是/是
頻率 - 最大： 133.33MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-PTQFP-EP（7x7）
包裝： 帶卷 (TR)
DATA SHEET
ICS8430S10BYI-02 REVISION C JANUARY 17, 2011
1
2011 Integrated Device Technology, Inc.
Clock Generator for Cavium Processors
ICS8430S10I-02
General Description
The ICS8430S10I-02 is a PLL-based clock generator specifically
designed for Cavium Networks SoC processors. This high
performance device is optimized to generate the processor core
reference clock, the DDR reference clocks, the PCI/PCI-X bus
clocks, and the clocks for both the Gigabit Ethernet MAC and PHY.
The clock generator offers ultra low-jitter, low-skew clock outputs,
and edge rates that easily meet the input requirements for the
CN30XX/CN31XX/CN38XX/CN58XX processors. The output
frequencies are generated from a 25MHz external input source or an
external 25MHz parallel resonant crystal. The extended temperature
range of the ICS8430S10I-02 supports telecommunication,
networking, and storage requirements.
Applications
Systems using Cavium Processors
CPE Gateway Design
Home Media Servers
802.11n AP or Gateway
Soho Secure Gateway
Soho SME Gateway
Wireless Soho and SME VPN Solutions
Wired and Wireless Network Security
Web Servers and Exchange Servers
Features
One selectable differential output pair for DDR 533/400/667,
LVPECL, LVDS interface levels
Nine LVCMOS/ LVTTL outputs, 20 typical output impedance
Selectable external crystal or differential (single-ended) input
source
Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
Differential input pair (CLK, nCLK) accepts LVPECL, LVDS, SSTL
input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
Power output supply modes
LVDS and LVPECL – full 3.3V
LVCMOS – full 3.3V or mixed 3.3V core/2.5V output
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
QC
48 47 46 45 44 43 42 41 40 39 38 37
V
QD0
QD1
GND
VDDO_B
QB0
VDD
nOE_D
GND
nPLL_ SEL
XTAL_IN
XTAL_OUT
nXTAL_SEL
CLK
nCLK
nOE_C
nOE_B
GND
V
DD
nO
E
_
A
nOE_REF
CORE_SEL
SP
I_
S
EL
1
SP
I_
SE
L0
DD
R
_
S
E
L
1
DD
R
_
S
E
L
0
PC
I_
S
E
L1
PC
I_
S
E
L0
V
DD
A
nLVD
S
_S
EL
48- Pin TQFP,E- Pad
7mm x 7mm x1mm
package body
Y Package
Top View
nQ
A
QA
V
DD
VDDO_B
QB1
DDO_CD
36
35
34
33
32
31
30
29
28
27
26
25
V
DD
O
_
R
E
F
nO
E
_
E
GN
D
GND
V
DD
O
_
R
E
F
QE
V
DD
O
_
E
GND
QREF2
QREF1
QREF0
ICS8430S10I-02
7mm x 7m x 1mm
package body
& Package
Top View
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS8430S10I-03 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Clock Generator for Cavium Processors
ICS8431-01 制造商:ICS 制造商全稱:ICS 功能描述:200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
ICS843101-312 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
ICS843101AG-312 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
ICS843101AG-312LF 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
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