參數(shù)資料
型號(hào)： ICS8430S10BYI-02LFT
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 31/31頁
文件大?。?/td> 0K
描述： IC CLK GENERATOR PLL 48TQFP
標(biāo)準(zhǔn)包裝： 1,000
類型： 時(shí)鐘/頻率發(fā)生器，扇出緩沖器（分配），多路復(fù)用器
PLL： 是
主要目的： Cavium 處理器
輸入： LVCMOS，LVDS，LVPECL，LVTTL，SSTL，晶體
輸出： LVCMOS，LVDS，LVPECL，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:10
差分 - 輸入:輸出： 是/是
頻率 - 最大： 133.33MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-PTQFP-EP（7x7）
包裝： 帶卷 (TR)
ICS8430S10BYI-02 REVISION C JANUARY 17, 2011
9
2011 Integrated Device Technology, Inc.
ICS8430S10I-02 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
AC Electrical Characteristics
Table 6. AC Characteristics, VDD = 3.3V ± 5%, VDDO_X = 3.3V ± 5% or 2.5V ± 5%, TA = -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at maximum fOUT unless noted otherwise.
NOTE: VDDO_X denotes VDDO_B, VDDO_CD, VDDO_E and VDDO_REF.
NOTE 1: Refer to the phase noise plot.
NOTE 2: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO_REF/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
fOUT
Output Frequency
QA, nQA
DDR_SEL[1:0] = 00
133.333
MHz
QA, nQA
DDR_SEL[1:0] = 01
100
MHz
QA, nQA
DDR_SEL[1:0] = 10
83.333
MHz
QA, nQA
DDR_SEL[1:0] = 11
125
MHz
QBx
CORE_SEL = 0
50
MHz
QBx
CORE_SEL = 1
33.333
MHz
QC
PCI_SEL[1:0] = 00
133.333
MHz
QC
PCI_SEL[1:0] = 01
100
MHz
QC
PCI_SEL[1:0] = 10
66.667
MHz
QC
PCI_SEL[1:0] = 11
33.333
MHz
QDx
SPI_SEL[1:0] = 00
100
MHz
QDx
SPI_SEL[1:0] = 01
125
MHz
QDx
SPI_SEL[1:0] = 10
80
MHz
QE
125
MHz
QREFx
25
MHz
tsk(b)
Bank Skew;
NOTE 2, 4
QREFx
30
ps
tsk(pp)
Part-to-Part Skew;
NOTE 3, 4
QREFx
200
ps
tjit(cc)
Cycle-to-Cycle Jitter
QA, nQA
measured at crosspoint
60
ps
QBx, QC, QDx
115
ps
QE
120
ps
tjit(per)
RMS Period Jitter
QA, nQA
measured at crosspoint
40
ps
tjit(hper)
RMS Half-period Jitter
QA, nQA
measured at crosspoint
50
ps
tjit()
RMS Phase Jitter,
(Random); NOTE 1
QREFx
25MHz (10kHz to 5MHz)
0.58
ps
QE
125MHz (1.875MHz to 20MHz)
0.72
ps
tR / tF
Output
Rise/Fall Time
QA, nQA
20% to 80%
100
300
ps
QBx, QC,
QDx, QE,
QREFx
400
1200
ps
odc
Output Duty Cycle
QA, nQA
48
52
%
QBx, QC,
QDx, QE,
QREFx
40
60
%
tLOCK
Lock Time
100
ms
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參數(shù)描述
ICS8430S10I-03 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Clock Generator for Cavium Processors
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