參數(shù)資料
型號: ICS8430S10BYI-02LFT
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 24/31頁
文件大?。?/td> 0K
描述: IC CLK GENERATOR PLL 48TQFP
標(biāo)準(zhǔn)包裝: 1,000
類型: 時鐘/頻率發(fā)生器,扇出緩沖器(分配),多路復(fù)用器
PLL:
主要目的: Cavium 處理器
輸入: LVCMOS,LVDS,LVPECL,LVTTL,SSTL,晶體
輸出: LVCMOS,LVDS,LVPECL,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 2:10
差分 - 輸入:輸出: 是/是
頻率 - 最大: 133.33MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-PTQFP-EP(7x7)
包裝: 帶卷 (TR)
ICS8430S10BYI-02 REVISION C JANUARY 17, 2011
30
2011 Integrated Device Technology, Inc.
ICS8430S10I-02 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Revision History Sheet
Rev
Table
Page
Description of Change
Date
B
T6
9
15
AC Characteristics Table - added Lock Time parameter.
Added Lock Time measurement drawing.
11/2/09
C
T4F
T9
1
2
8
16
17
18
19
21
28
Features section - corrected Differential Input bullet (deleted HCSL and LVHSTL levels).
Block Diagram - corrected naming convention for SPI4_SEL1:0 to SPI_SEL1:0.
Differential DC Characteristics Table - corrected VCMR levels from
0.5V min / VDD - 0.85V max to 1.2V min / VDD max.
Deleted Power Supply Filtering Technique application note (see Schematic Example).
Updated Wiring the Differential Input to Accept Single-ended Levels application note.
Corrected Differential Clock Input Interface application note (deleted HCSL and LVHSTL
levels).
Deleted Crystal Input Interface application note (see Schematic Example).
Updated Overdriving the XTAL Interface application note.
Updated LVDS Driver Termination application note.
Updated Schematic Example application note and diagram.
Corrected D3/E3 dimensions. Updated Package Outline.
1/17/11
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