參數資料
型號: ICS8430S10BYI-02LFT
廠商: IDT, Integrated Device Technology Inc
文件頁數: 19/31頁
文件大小: 0K
描述: IC CLK GENERATOR PLL 48TQFP
標準包裝: 1,000
類型: 時鐘/頻率發(fā)生器,扇出緩沖器(分配),多路復用器
PLL:
主要目的: Cavium 處理器
輸入: LVCMOS,LVDS,LVPECL,LVTTL,SSTL,晶體
輸出: LVCMOS,LVDS,LVPECL,LVTTL
電路數: 1
比率 - 輸入:輸出: 2:10
差分 - 輸入:輸出: 是/是
頻率 - 最大: 133.33MHz
電源電壓: 3.135 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TQFP 裸露焊盤
供應商設備封裝: 48-PTQFP-EP(7x7)
包裝: 帶卷 (TR)
ICS8430S10BYI-02 REVISION C JANUARY 17, 2011
26
2011 Integrated Device Technology, Inc.
ICS8430S10I-02 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
The LVPECL output driver circuit and termination are shown in Figure 8.
Figure 8. LVPECL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of
VDDO – 2V.
For logic high, VOUT = VOH_MAX = VDDO_MAX – 0.9V
(VDDO_MAX – VOH_MAX) = 0.9V
For logic low, VOUT = VOL_MAX = VDDO_MAX – 1.7V
(VDDO_MAX – VOL_MAX) = 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(VOH_MAX – (VDDO_MAX – 2V))/RL] * (VDDO_MAX – VOH_MAX) = [(2V – (VDDO_MAX – VOH_MAX))/RL] * (VDDO_MAX – VOH_MAX) =
[(2V – 0.9V)/50
] * 0.9V = 19.8mW
Pd_L = [(VOL_MAX – (VDDO_MAX – 2V))/RL] * (VDDO_MAX – VOL_MAX) = [(2V – (VDDO_MAX – VOL_MAX))/RL] * (VDDO_MAX – VOL_MAX) =
[(2V – 1.7V)/50
] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
V
OUT
V
DDO
V
DDO - 2V
Q1
RL
50
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