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參數(shù)資料
| 型號(hào)： | ICS8430S10BYI-02LFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 17/31頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK GENERATOR PLL 48TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，扇出緩沖器（分配），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | Cavium 處理器 |
| 輸入： | LVCMOS，LVDS，LVPECL，LVTTL，SSTL，晶體 |
| 輸出： | LVCMOS，LVDS，LVPECL，LVTTL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 133.33MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-PTQFP-EP（7x7） |
| 包裝： | 帶卷 (TR) |
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ICS8430S10BYI-02 REVISION C JANUARY 17, 2011
24
2011 Integrated Device Technology, Inc.
ICS8430S10I-02 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Power Considerations (LVCMOS/LVPECL Outputs)
This section provides information on power dissipation and junction temperature for the ICS8430S10I-02.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS8430S10I-02 is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
Core and LVPECL Output Power Dissipation
Power (core)_MAX = VDD_MAX * IEE_MAX = 3.465V * 180mA = 623.7mW
Power (output)_MAX = 30mW/Loaded Output Pair
LVCMOS Output Power Dissipation
Output Impedance ROUT Power Dissipation due to Loading 50 to VDDO/2
Output Current IOUT = VDDO_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 20)] = 24.80mA
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)
2 = 20
* (24.80mA)2 = 12.3mW per output
Total Power Dissipation on the ROUT
Total Power (ROUT) = 12.3mW * 9 = 110.7mW
Dynamic Power Dissipation at 133MHz
Power (133MHz) = CPD * Frequency * (VDDO)
2 = 10pF * 133MHz * (3.465V)2 = 16mW per output
Total Power (133MHz) = 16mW * 6 = 96mW
Dynamic Power Dissipation at 25MHz
Power (25MHz) = CPD * Frequency * (VDDO)
2 = 10pF * 25MHz * (3.465)2 = 3mW per output
Total Power (25MHz) = 3mW * 3 = 9mW
Total Power Dissipation
Total Power
= Power (core) + Power (LVPECL output) + Total Power (ROUT) + Total Power (133MHz) + Total Power (25MHz)
= 623.7mW + 30mW + 110.7mW + 96mW + 9mW
= 869.4mW
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS8430S10I-03 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Clock Generator for Cavium Processors |
| ICS8431-01 | 制造商:ICS 制造商全稱:ICS 功能描述:200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER |
| ICS843101-312 | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101AG-312 | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| ICS843101AG-312LF | 制造商:ICS 制造商全稱:ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
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