參數(shù)資料
型號(hào)： ICS8430S10BYI-02LFT
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 11/31頁(yè)
文件大?。?/td> 0K
描述： IC CLK GENERATOR PLL 48TQFP
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 時(shí)鐘/頻率發(fā)生器，扇出緩沖器（分配），多路復(fù)用器
PLL： 是
主要目的： Cavium 處理器
輸入： LVCMOS，LVDS，LVPECL，LVTTL，SSTL，晶體
輸出： LVCMOS，LVDS，LVPECL，LVTTL
電路數(shù)： 1
比率 - 輸入:輸出： 2:10
差分 - 輸入:輸出： 是/是
頻率 - 最大： 133.33MHz
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-TQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 48-PTQFP-EP（7x7）
包裝： 帶卷 (TR)
ICS8430S10BYI-02 REVISION C JANUARY 17, 2011
19
2011 Integrated Device Technology, Inc.
ICS8430S10I-02 Data Sheet
CLOCK GENERATOR FOR CAVIUM PROCESSORS
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
The differential output pair is low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be used
to maximize operating frequency and minimize signal distortion.
Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and clock
component process variations.
Figure 4A. 3.3V LVPECL Output Termination
Figure 4B. 3.3V LVPECL Output Termination
LVDS Driver Termination
A general LVDS interface is shown in Figure 5. Standard termination
for LVDS type output structure requires both a 100
parallel resistor
at the receiver and a 100
differential transmission line environment.
In order to avoid any transmission line reflection issues, the 100
resistor must be placed as close to the receiver as possible. IDT
offers a full line of LVDS compliant devices with two types of output
structures: current source and voltage source. The standard
termination schematic as shown in Figure 5 can be used with either
type of output structure. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output is a current
source or a voltage source type structure. In addition, since these
outputs are LVDS compatible, the amplitude and common mode
input range of the input receivers should be verified for compatibility
with the output.
Figure 5. Typical LVDS Driver Termination
3.3V
V
CC - 2V
R1
50
R2
50
RTT
Z
o = 50
Z
o = 50
+
_
RTT =
* Z
o
1
((V
OH + VOL) / (VCC – 2)) – 2
3.3V
LVPECL
Input
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o = 50
Z
o = 50
LVPECL
Input
3.3V
+
_
100
–
+
100
Differential Transmission Line
LVDS Driver
LVDS
Receiver
相關(guān)PDF資料
PDF描述
VI-B1L-IU CONVERTER MOD DC/DC 28V 200W
VI-B1D-IU CONVERTER MOD DC/DC 85V 200W
VE-2N4-MX-F4 CONVERTER MOD DC/DC 48V 75W
MS3106A28-12S CONN PLUG 26POS STRAIGHT W/SCKT
MS3451W14S-5P CONN RCPT 5POS CBL MNT W/PINS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS8430S10I-03 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:Clock Generator for Cavium Processors
ICS8431-01 制造商:ICS 制造商全稱(chēng):ICS 功能描述:200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER
ICS843101-312 制造商:ICS 制造商全稱(chēng):ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
ICS843101AG-312 制造商:ICS 制造商全稱(chēng):ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
ICS843101AG-312LF 制造商:ICS 制造商全稱(chēng):ICS 功能描述:FEMTOCLOCKS⑩ CRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*