參數(shù)資料
型號: IBM25EMPPC603EBG-100
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255
封裝: 21 X 21 MM, 1.27 MM PITCH, 3 MM HEIGHT, CERAMIC, BGA-255
文件頁數(shù): 5/42頁
文件大小: 509K
代理商: IBM25EMPPC603EBG-100
603e and EM603e Hardware Specification
13
19
SYSCLK to ARTRY precharge enable
0.2 *
tsysclk
+ 1.0
0.2 *
tsysclk
+ 1.0
0.2 *
tsysclk
+ 1.0
ns
2,4,7
20
Maximum delay to ARTRY precharge
1.2
1.0
1.0
tsysclk
4,7
21
SYSCLK to ARTRY high impedance after
precharge
2.25
2.0
2.0
tsysclk
5,7
Notes:
1. All output specications are measured from the 1.4 V of the rising edge of SYSCLK to the TTL level (0.8 V or 2.0 V)
of the signal in question. Both input and output timings are measured at the pin (see Figure 4).
2. This minimum parameter assumes CL = 0 pF.
3. SYSCLK to output valid (5.5 V to 0.8 V) includes the extra delay associated with discharging the external voltage
from 5.5 V to 0.8 V instead of from Vdd to 0.8 V (5-V CMOS levels instead of 3.3-V CMOS levels).
4. tsysclk is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must
be multiplied by the period of SYSCLK to compute the actual time duration (in nanoseconds) of the parameter in
question.
5. Output signal transitions from GND to 2.0 V or Vdd to 0.8 V.
6. Nominal precharge width for ABB and DBB is 0.5 tsysclk.
7. Nominal precharge width for ARTRY is 1.0 tsysclk.
Table 9. Output AC Timing Specifications1 (Continued)
Vdd = AVdd = 2.5
± 5% Vdc (= 3.3 ± 5% Vdc for PID6). O Vdd = 3.3 ± 5% Vdc. GND = 0 Vdc, 0 ≤ Tj ≤ 105 °C. CL = 50 pF (unless otherwise
noted) (PID6 maximum timing specications assume CL = 50pF).
PID6
PID7v
PID7t
Num
Characteristic
80 MHz
100 MHz
166 MHz
200 MHz
Unit Notes
Min
Max
Min
Max
Min
Max
Min
Max
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