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參數(shù)資料
| 型號： | IBM25EMPPC603EBG-100 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, CBGA255 |
| 封裝： | 21 X 21 MM, 1.27 MM PITCH, 3 MM HEIGHT, CERAMIC, BGA-255 |
| 文件頁數(shù)： | 41/42頁 |
| 文件大?。?/td> | 509K |
| 代理商： | IBM25EMPPC603EBG-100 |
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8
603e and EM603e Hardware Specification
1.4.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the 603e and EM603e. The processor core
frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0–3] signals.
All timings are specied respective to the rising edge of SYSCLK. PLL_CFG signals should be set prior to
power up and not altered afterwards.
1.4.2.1 Clock AC Specications
Table 7 provides the clock AC timing specications as dened in Figure 1. After fabrication, parts are sorted
by maximum processor core frequency as shown in Section 1.4.2.1, “Clock AC Specications” and tested
for conformance to the AC specications for that frequency. Parts are sold by maximum processor core
frequency; see Section 1.9, “Ordering Information.”
Notes:
1.These values apply for all valid PLL_CFG[0–3] settings and do not include output driver power
(OVdd) or analog supply power (AVdd). OVdd power is system dependent but is typically
≤ (< only
for PID6) 10% of Vdd. Worst-case AVdd = 15 mW.
2. Typical power is an average value measured at Vdd = AVdd = 2.5 V, OVdd = 3.3V (Vdd = AVdd =
OVdd = 3.3 V for PID6), in a system executing typical applications and benchmark sequences.
3. Maximum power is measured at 2.625 V (3.465 V for PID6) using a worst-case instruction mix.
Table 7. Clock AC Timing Specifications
Vdd = AVdd = 2.5
± 5% Vdc (= 3.3 ± 5% Vdc for PID6). O Vdd = 3.3 ± 5% Vdc. GND = 0 Vdc, 0 ≤ Tj ≤ 105°C.
Num
Characteristic
PID6
PID7v
PID7t
Unit
Notes
80 MHz
100 MHz
166 MHz
200 MHz
Min
Max
Min
Max
Min
Max
Min
Max
Processor
frequency
80
85
100
150
166
200
MHz
1
VCO
frequency
100
200
100
200
250
333
250
400
MHz
1
SYSCLK (bus)
frequency
16.67
66.67
16.67
66.67
25
66.67
25
66.67
MHz
1
SYSCLK cycle
time
15.0
60.0
15.0
60.0
15.0
40.0
15
40.0
ns
2,3
SYSCLK rise
and fall time
—
2
—
2.0
—
2.0
—
2.0
ns
2
Table 6. Power Consumption1 (Continued)
Processor (CPU) Frequency
Unit
PID6
PID7v
PID7t
80 MHz
100 MHz
166 MHz
200 MHz
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