
603e and EM603e Hardware Specification
37
For a power dissipation of 2.5 Watts in an ambient temperature of 40
°C at 1 m/sec with the pinn heatsink
measured above, the junction temperature of the device is well within the reliability limits as follows:
Tj = Ta + Rθja * P
Tj = 40°C + (9.1°C/Watt * 2.5 Watts) = 63°C
Notes:
1. Junction-to-ambient thermal resistance is based on modeling.
2. Junction-to-heatsink thermal resistance is based on measurements and model using thermal test
chip and thermal couple which is placed on the base of the heatsink.
3.
θ
ja is not measured for 0.25 m/sec convection for the pinn.
The vendors who supply heatsinks are Aavid Engineering, Thermalloy, and Wakeeld Engineering. Any of
these vendors can supply heatsinks with sufcient thermal performance. The following list contains contact
information.
The vendors who supply heatsinks are Aavid Engineering, IERC, Thermalloy, and Wakeeld Engineering.
Contact information for these vendors follows:
Thermalloy
972-243-4321
2021 W. Valley View Lane
http://www.thermalloy.com
P.O. Box 810839
Dallas, TX 75731
International Electronic Research Corporation (IERC)
818-842-7277
135 W. Magnolia Blvd.
Burbank, CA 91502
Aavid Engineering
603-528-3400
One Kool Path
http://www.aavid.com
Laconic, NH 03247-0440
Wakeeld Engineering
781-406-3000
60 Audubon Rd.
www.wakeeld.com
Wakeeld, MA 01880
Any of these vendors can supply heatsinks with sufcient thermal performance.
1.8.6.2 CBGA Package
The data found in this section concerns 603e’s and EM603e’s packaged in the 255-lead 21 mm multi-layer
ceramic (MLC), CBGA package. Data is shown for two cases, the exposed-die case (no heatsink) and using
the Thermalloy 2338-pin n heatsink.
1.8.6.2.1 Thermal Characteristics
The internal thermal resistance for this package is negligible due to the exposed die design. A heatsink is
attached directly to the silicon die surface only when external thermal enhancement is necessary.
Additionally, the CBGA package offers an exceptional thermal connection to the card and power planes.
Heat generated at the chip is dissipated through the package, the heatsink (when used) and the card. The
parallel heat ow paths result in the lowest overall thermal resistance as well as offer signicantly better
power dissipation capability when a heatsink is not used.