參數(shù)資料
型號： IBM025170
廠商： IBM Microeletronics
英文描述： 4Mb（256K X 16） MULTIPORT VIDEO RAM(4M位（256K X 16）多端口視頻RAM)
中文描述： 4Mb的（256 × 16）多端口視頻內(nèi)存（4分位（256 × 16）多端口視頻內(nèi)存）
文件頁數(shù)： 57/65頁
文件大?。?/td> 841K
代理商： IBM025170
IBM025160
IBM025161
IBM025170
IBM025171
256K X 16 MULTIPORT VIDEO RAM
33G0307
SA14-4751-05
Revised 3/98
IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 57 of 65
Serial Register Stop (SRS) Mode
The SRS mode is very useful in applications where the DRAM data is arranged in the form of tiles and the
Serial port is read out in scan line order. A typical case is that of vectors that cross many scan lines on the
screen. The pixels for vector(s) can be written in a single row or minimum number of rows depending on the
tile width using page mode cycles. A detailed explanation is given in the Application Note, “Read/Write Trans-
fer Operation”. The SRS mode is set by executing CBRS cycle just after power up. The 4-Mb VRAM has an
8-bit Stop Register. The Stop Register value is latched at the falling edge of RE during CBRS cycle using
address inputs A
4
-A
7
(A
0
-A
3
and A
8
are don't care). Up to eight different stop positions or boundaries can be
specified for each half of SAM as shown in the Stop Register Set table on page 57 by invoking a CBRS cycle.
Note: If the Serial port counter is between 128 and 255, the STOP address is equal to 128 plus the
number(s) specified in column 3 of the Stop Register Set table on page 57. When the counter reaches
the STOP address, the counter is loaded with the TAP point register address that was saved during
the Split Transfer cycle
For more details of the Stop Column control for the Serial Port, refer to the Application Note, “Read/Write
Transfer Operation”. Another application of SRS mode is to make “Half Depth SAM” VRAM part compatible to
“Full Depth SAM” VRAM parts. Full compatibility is provided between Half Depth SAM and Full Depth SAM by
performing split transfer in SRS mode using STOP address of 127 or less. For more details, refer to Applica-
tion Note, “Half SAM and Full SAM Compatibility”.
Full Register Read Transfer (SRS) Mode
A Full Read Transfer in SRS mode will transfer 256 x16 bits from the selected row based on CA
7
at CE fall
time during the Full Read Transfer cycle. CA
8
is a don't care. If CA
7
is “0”, data from locations in the selected
row having physical address CA
7
equal to “0” is transferred to SAM. If CA
7
is “1”, data from locations that
have a physical address CA
7
equal to “1” is transferred to SAM. Note that the data corresponding to physical
address CA
8
equal to “0” is associated with the lower half of SAM while the data corresponding to physical
address CA
8
equal to “1" in a row is associated with the upper half of SAM. The timing diagram on page 58
illustrates a Full Read Transfer in SRS mode between DRAM and SAM.
Stop Register Set
Address
by User
A
8
- A
0
Stop Register
Value:
A
7
- A
0
If the Serial port counter is less than 128, the
STOP address is equal to whichever occurs first
X 1111 XXXX
X 0111 XXXX
X 0011 XXXX
X 0001 XXXX
0111 1111
0011 1111
0001 1111
0000 1111
127
63,127
31,63,95,127
15,31,47,63,79,95,111,127
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