參數(shù)資料
型號： IBM025170
廠商： IBM Microeletronics
英文描述： 4Mb（256K X 16） MULTIPORT VIDEO RAM(4M位（256K X 16）多端口視頻RAM)
中文描述： 4Mb的（256 × 16）多端口視頻內(nèi)存（4分位（256 × 16）多端口視頻內(nèi)存）
文件頁數(shù)： 11/65頁
文件大小： 841K
代理商： IBM025170
IBM025160
IBM025161
IBM025170
IBM025171
256K X 16 MULTIPORT VIDEO RAM
33G0307
SA14-4751-05
Revised 3/98
IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 65
AC Characteristics
(T
A
= 0 to +70
°
C)
Read, Write, Read-Modify-Write and Refresh. Cycles (Part 1 of 2)
(Common Parameters)
Symbol
Parameter
-6H
-60
-70
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
t
ASC
Column address setup time
0
—
0
—
0
—
ns
t
ASR
Row address setup time
0
—
0
—
0
—
ns
t
AR
Column address hold time after RE low
15
—
20
—
25
—
ns
t
CAH
Column address hold time after CE low
6
—
6
—
8
—
ns
5
t
CAS
CE pulse width
12
16K
15
16K
17
16K
ns
t
CHCL
First CE to return high to last CE going low
6
—
6
—
8
—
ns
t
CLCH
Last CE going low to first CE to return high
6
—
6
—
8
—
ns
t
CP
CE precharge time
6
—
6
—
8
—
ns
t
CRP
CE high before RE low precharge
5
—
5
—
10
—
ns
8
t
CSH
CE hold time
60
—
60
—
70
—
ns
t
H(SFC)
DSF hold time after CE low
6
—
6
—
8
—
ns
t
H(SFR)
DSF hold time after RE low
6
—
6
—
8
—
ns
t
MH
Write mask hold time after RE low
6
—
6
—
8
—
ns
t
MS
Data-in setup before RE low
0
—
0
—
0
—
ns
t
RAD
RE to column address delay time
11
35
11
35
13
40
ns
4
t
RAH
Row address hold time after RE low
6
—
6
—
8
—
ns
t
RAS
RE pulse width
60
100K
60
100K
70
100K
ns
t
RC
,t
WC
Random read or write cycle time
95
—
95
—
110
—
ns
1, 2
t
RCD
Delay from RE low to CE low
16
45
16
45
18
53
ns
3, 5, 9
t
RP
RE precharge time
25
—
25
—
30
—
ns
1, 6, 7
t
RSH
RE hold time
15
—
15
—
17
—
ns
t
RWH
W hold time after RE low
6
—
6
—
8
—
ns
t
SU(SFC)
DSF setup time before CE low
0
—
0
—
0
—
ns
1. An initial pause of 100
μ
s is required after power up followed by 8 CE before RE refresh cycles for proper device operation
2. AC measurements assume t
T
= 5ns.
3. Operation within the t
RCD
(max) limit ensures that t
RAC
(max.) can be met. t
RCD
(max.) is specified as a reference point only: If t
RCD
is greater than the specified t
RCD
(max) limit, then access time is controlled by t
CAC
.
4. Operation within the t
RAD
(max) limit ensures that t
RAC
(max.) can be met. t
RAD
(max.) is specified as a reference point only: If t
RAD
is greater than the specified t
RAD
(max) limit, then access time is controlled by t
AA
.
5. t
RCD
and t
CAH
cannot be at minimum values simultaneously. t
RCD
+ t
CAH
≥
45ns (60ns t
RAC
product), t
RCD
+ t
CAH
≥
50ns (70ns
t
RAC
product).
6. t
RWL
and t
RP
cannot be at minimum values simultaneously. t
RW
L + t
RP
≥
60ns (60ns t
RAC
product), t
RWL
+ t
RP
≥
70ns (70ns t
RAC
product).
7. t
CWL
and t
RP
cannot be at minimum values simultaneously. t
CWL
+ t
RP
≥
60ns (60ns t
RAC
product), t
CWL
+ t
RP
≥
70ns (70ns t
RAC
product).
8. t
CRP
must be 15ns (60ns t
RAC
) or 17ns (70ns t
RAC
) if a write-per-bit mask is used on the following RE cycle due to the fact that t
OFF
must be met.
9. During Serial port write transfer t
RCD
(max) = 100ns.
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