參數(shù)資料
型號(hào)： IBM025170
廠商： IBM Microeletronics
英文描述： 4Mb（256K X 16） MULTIPORT VIDEO RAM(4M位（256K X 16）多端口視頻RAM)
中文描述： 4Mb的（256 × 16）多端口視頻內(nèi)存（4分位（256 × 16）多端口視頻內(nèi)存）
文件頁數(shù)： 46/65頁
文件大?。?/td> 841K
代理商： IBM025170
IBM025170
IBM025171
256K X 16 MULTIPORT VIDEO RAM
IBM025160
IBM025161
IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 46 of 65
33G0307
SA14-4751-05
Revised 3/98
Functional Description
The DRAM array is organized as 512 rows x 512 columns x 16 bit wide. The device is capable of performing
normal Read/Write operations similar to a DRAM. Besides fast page Read/Write, the 4-Mb VRAM has the fol-
lowing added functions:
Full Register Read Transfer
Split Register Read Transfer
Full Register Write Transfer
Split Register Write Transfer
8 Column Block Write
Full Row Flash Write
Extended Data Out (EDO)
Serial Port Read
Serial Port Write
Power Up or VRAM Initialize Process
After V
CC
has reached its regulated value, allow at least 100
μ
s for build up of N-well voltage inside the chip.
Perform at least 8 CAS-Before-RAS (CBR) refresh cycles to reset unwanted mode(s) which may be set dur-
ing power up. For more details refer to the Application Note, “Designing with 4-Mb VRAM”.
The Serial port
will be initialized with the jump address of 128 bit at power up, thereby requiring no STOP address
setting by the user for split Read or split Write in normal mode operations
.
DRAM Refresh Operation
DRAM array consists of volatile cells, therefore these cells need to be refreshed periodically. The minimum
rate for VRAM is 512 refresh cycles every 32ms. Every cell therefore gets a chance to be refreshed every 32
ms. The SAM Registers memory is static in nature and therefore requires no refresh.
The following refresh modes are available in IBM's 4-Mb VRAM:
RE Only Refresh (ROR)
A cycle having only RE active refreshes all cells in one row of the storage array. A high CE is maintained
while RE is active to keep DQs in high impedance.
Note that the row address for refresh is supplied by the user.
RE only Refresh mode will not clear any
unknown modes at power up. Therefore, CBR cycles at power up must be performed to clear any
unknown modes
. The timing diagram on page 37 shows a RE only Refresh mode.
CE before RE Refresh (CBR)
The CBR Refresh mode is selected by bringing the CE low before RE is brought low and keeping DSF low as
shown in the timing diagram on page 38. An internal address counter selects the row to be refreshed.
CBR
cycle will reset any special modes set by CBRS or any persistent mask
. Note that DQs are in high-Z
state during CBR cycle.
CE before RE Refresh without mode Reset (CBRN)
CBRN mode is set by bringing CE low before RE is brought low and keeping W and DSF high at the falling
edge of RE. The internal counter selects the row to be refreshed
. CBRN will neither clear any special
modes set by the CBRS cycle nor any masks
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