參數(shù)資料
型號(hào)： IBM025170
廠商： IBM Microeletronics
英文描述： 4Mb（256K X 16） MULTIPORT VIDEO RAM(4M位（256K X 16）多端口視頻RAM)
中文描述： 4Mb的（256 × 16）多端口視頻內(nèi)存（4分位（256 × 16）多端口視頻內(nèi)存）
文件頁(yè)數(shù)： 52/65頁(yè)
文件大?。?/td> 841K
代理商： IBM025170
IBM025170
IBM025171
256K X 16 MULTIPORT VIDEO RAM
IBM025160
IBM025161
IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 52 of 65
33G0307
SA14-4751-05
Revised 3/98
Split Register Read Transfer (Normal) Mode
The Split Read Transfer is used to read data continuously from the Serial port without having to worry about
synchronizing the SC clock with the operation of the primary port. This transfer operation loads 128 x16 bits
of a wordline into half of the SAM. The user supplied column address bit “CA
8
” and an internally generated
“CA
7
” determines which quarter of the word line is transferred to the SAM.
Note the user supplied “CA
7
” at CE fall time during transfer cycle is a don't care and is internally generated
based on which half of the SAM is active. This way, the inactive half of SAM can be loaded with the new data
while data is being read out of the other active half. The start address is given by CA
6
- CA
0
but is held in a
TAP address pointer register until the serial counter reaches the jump address (127/255). At that point, the
start address register is loaded with the address from the TAP address register. The Serial port counter will
also be loaded with this address at the same time. The reading of data will start from this address in the other
half of SAM that was previously inactive at the next SC clock. The Split Read Transfer in normal mode is illus-
trated in the timing diagram on page 43.
The example in the timing diagram on page 53 illustrates a Split Read Transfer between DRAM and SAM
based on user supplied CA
8
during Split Read Transfer cycle and an internally generated CA
7
. In the first
example (CA
8
= 1), the Serial port is active reading data from the upper half of the SAM while the lower half of
SAM is idling. Therefore, CA
7
is internally changed to “0” and the transfer is forced to lower half of SAM. In
the second example, the Serial port is active reading data from the lower half of SAM, the transfer is therefore
forced to the upper half of SAM.
Note: There must be a Full Read Transfer prior to any Split Read Transfer. After the Full Read Trans-
fer, any number of Split Read Transfers can be performed. The Split Read Transfer can be initiated to
the idling part of SAM at any time while the active half is being read. It is generally a good practice to
perform a Split Read Transfer to the idle half of SAM at any time way ahead of the last data being read
out of the active half of SAM
.
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