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| 型號(hào)： | IBM025160 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4Mb（256K X 16） MULTIPORT VIDEO RAM(4M位（256K X 16）多端口視頻RAM) |
| 中文描述： | 4Mb的（256 × 16）多端口視頻內(nèi)存（4分位（256 × 16）多端口視頻內(nèi)存） |
| 文件頁數(shù)： | 47/65頁 |
| 文件大?。?/td> | 841K |
| 代理商： | IBM025160 |
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IBM025160
IBM025161
IBM025170
IBM025171
256K X 16 MULTIPORT VIDEO RAM
33G0307
SA14-4751-05
Revised 3/98
IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 47 of 65
CE before RE Refresh with Stop Register Set (CBRS)
The CBRS operation is selected by bringing W and CE low before RE is brought low and keeping DSF high
as shown in the timing diagram on page 40. An internal address counter selects the row to be refreshed. This
cycle is also used to set the chip into Serial Register Stop mode (SRS). Full compatibility is provided between
Half Depth SAM and Full Depth SAM by performing Split Transfer in SRS mode using STOP address of 127
or less. For more details, refer to Application Note, “Half SAM and Full SAM Compatibility”.
Recommended CBR, CBRS, and CBRN Cycles
To ensure that the device has not entered unwanted register modes at power up, at least
eight CBR cycles
must be executed before normal operation of the device is resumed
. A CBR after each vertical retrace is
recommended. This fail-safe routine is for cases where a system misoperation causes entry into an unwanted
mode. If the STOP Register function is used, then a CBRS must be invoked following every CBR cycle. If the
STOP register function is not required and Persistent Write masking is employed, then use a CBRN. CBRN
does not clear the old mask.
Byte Control
The 4-Mb VRAM is available with either Dual W or Dual CE. A dual CE part has lower and upper byte control.
The LCE controls the DQ
0
-DQ
7
while UCE controls DQ
8
- DQ
15
. Individual byte control can be applied during
read and write operations on the primary port.
A dual W part has a lower and upper W. The LW and UW allow individual byte control of the DQs during write
operations. The LW controls DQ
0
-DQ
7
and UW controls DQ
8
- DQ
15
. Individual byte control can be applied
to the DRAM Read, Write, Block Write, Load Mask Register and Load Color Register cycles.
Read Cycle
A Read cycle is executed by activating RE, CE, and TRG and by maintaining W high while CE is active. The
DQs remain in high-Z until valid data appears at the output at access time. Device access time, t
ACC
, will be
the longest of the four calculated intervals:
t
RAC
Access time from RE falling edge
t
RCD
(RE to CE delay) + t
CAC
(Access time from CE falling edge)
t
RAD
(RE to Column Address delay) + t
AA
(Access time from column Address)
RE to TRG delay + t
OEA
(Access time from TRG)
Device dependent parameters are: t
RAC
, t
CAC
, t
AA
and t
OEA
. System dependent parameters are: t
RCD
, t
RAD
and RE to TRG delay. Output becomes valid after the access time has elapsed. It remains valid while CE and
TRG are low (Fast Page parts only). It remains valid while TRG is low (EDO parts only). Either CE or TRG
high returns the output pins to high-Z (Fast Page parts only). TRG high returns the output pins to high-Z (EDO
parts only).
Write Cycle
A Write cycle is executed by bringing W low during RE/CE cycle. The falling edge of CE or W whichever
occurs later strobes the data on DQ pins into the on-chip data latch.
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