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參數(shù)資料
| 型號： | IBM025161 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4Mb（256K X 16） MULTIPORT VIDEO RAM(4M位（256K X 16）多端口視頻RAM) |
| 中文描述： | 4Mb的（256 × 16）多端口視頻內(nèi)存（4分位（256 × 16）多端口視頻內(nèi)存） |
| 文件頁數(shù)： | 1/65頁 |
| 文件大?。?/td> | 841K |
| 代理商： | IBM025161 |
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IBM025160
IBM025161
IBM025170
IBM025171
256K X 16 MULTIPORT VIDEO RAM
33G0307
SA14-4751-05
Revised 3/98
IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 65
Features
256K x 16 Multiport Video RAM
Performance:
Fully Asynchronous operation of Random port
and Serial port
Compatible to Full Depth SAM in SRS mode
8 Column Block Write with masking Column and
WPB masking along with individual Byte Control
Parameter
-6H
-60
-70
t
RP
RE
Precharge
25ns
25ns
30ns
t
SCA
Serial Access Time
12ns
15ns
17ns
t
CAC
Access Time from
CE
15ns
15ns
17ns
t
AA
Column Address Access Time
25ns
30ns
35ns
t
SCC
Serial Clock Cycle Time
12ns
18ns
20ns
t
RC
Read or Write Cycle Time
95ns
95ns
110ns
t
PC
Fast Page Mode Cycle Time
30ns
30ns
40ns
t
HPC
Extended Data Out Cycle Time
20ns
25ns
30ns
50 MHz EDO performance
FLASH WRITE with WPBM- 512 x 16 bits
Persistent & Non-Persistent WPBM mode
Split Serial Register with Width Control
256 Location Start Address Pointer for SAM
Full Read and Split Read Transfer
Masked Write Transfer
Masked Split Write Transfer
Power Supply: 5.0V
±
0.5V and 3.3V
±
0.3V
High Performance, CMOS 0.55
μ
m process
SSOG-64 JEDEC Standard
TTL compatible
Description
This 4Mb dual port Video RAM (VRAM) consists of a
Dynamic Random Access Memory (DRAM) orga-
nized as 256K x 16 interfaced to a Serial Register /
Serial Access Memory (SAM) organized as 256 x
16. The VRAM supports three basic operations:
Bidirectional Random Access to the DRAM, Bidirec-
tional Serial Access to the SAM, and Bidirectional
Data Transfer between any DRAM row and the
SAM. Full compatibility is provided between Half
Depth SAM (256 x 16) and Full Depth SAM (512 x
16) by setting the VRAM in Serial Register Stop
(SRS) mode with a stop address of 128 bit (or less).
Unique features have been added to these basic
VRAM operations to improve graphics performance
of the system. Higher update rates can be achieved
with either Flash Write or Block Write modes. Two
W
or two
CE
inputs are provided for individual byte con-
trol for both normal Write and Block Write. For indi-
vidual bit control, a Write-Per-Bit Mask (WPBM) can
be supplied on the data pins at
RE
time to be used
during Masked Write transfers or Masked Write
cycles. A permanent mask to be used during Block
Write cycles can be loaded using the Load Mask
Register (LMR) cycle.
IBM025160256 x 16FP, 2CE. IBM025171256 x 16EDO, 2WE. IBM025170256 x 16FP, 2WE. IBM025161256 x 16EDO, 2CE.
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