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| 型號： | IBM025161 |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4Mb（256K X 16） MULTIPORT VIDEO RAM(4M位（256K X 16）多端口視頻RAM) |
| 中文描述： | 4Mb的（256 × 16）多端口視頻內(nèi)存（4分位（256 × 16）多端口視頻內(nèi)存） |
| 文件頁數(shù)： | 60/65頁 |
| 文件大小： | 841K |
| 代理商： | IBM025161 |
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IBM025170
IBM025171
256K X 16 MULTIPORT VIDEO RAM
IBM025160
IBM025161
IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 60 of 65
33G0307
SA14-4751-05
Revised 3/98
Write Transfer (SRS) Modes
Full Register Write Transfer (SRS) Mode
The Full Register Write Transfer operation in SRS mode is illustrated in the timing diagram on page 60. This
operation will store the entire contents of the SAM in the row specified by row address (RA
8
- RA
0
) at RE fall
time and CA
7
at CE fall time during the Full Register Write Transfer cycle in SRS mode. CA
7
controls the
transfer of data to the particular segments of the row. If CA
7
at CE fall time during a Full Register Transfer
cycle is “1”, the data from SAM is stored in those segments of the row whose physical address bit “CA
7
”
equals to “1”. Data from the lower half of SAM is transferred to locations in the row that have physical address
CA
8
equal to “0”, data from the upper half of SAM is transferred to locations in the row that have physical
address CA
8
equal to “1”. CA
7
-CA
0
address supplied by the user at CE fall time is loaded in the start address
register to be used as starting location for writing the data in the Serial port on the next SC clock following the
transfer. During the Full Register Write Transfer cycle, a WPBM can be loaded at RE fall time to mask the
selected data bits at transfer time.
Generally, it is a good practice to mask all the data bits at the first Full
Register Write Transfer cycle to prevent writing of old data left over from previous Read Transfer
operations.
The example illustrates a full transfer in SRS mode based on CA
7
=1.
Full Register Write Transfer (SRS) Mode
Array
511
Rows
Cols
SAM
0
127
128
255
0
383
511
255
127
CA
7
=0 CA
8
=0
CA
7
=1 CA
8
=0
CA
7
=0 CA
8
=1
CA
7
=1 CA
8
=1
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