參數(shù)資料
型號： IBM025161
廠商： IBM Microeletronics
英文描述： 4Mb（256K X 16） MULTIPORT VIDEO RAM(4M位（256K X 16）多端口視頻RAM)
中文描述： 4Mb的（256 × 16）多端口視頻內(nèi)存（4分位（256 × 16）多端口視頻內(nèi)存）
文件頁數(shù)： 48/65頁
文件大?。?/td> 841K
代理商： IBM025161
IBM025170
IBM025171
256K X 16 MULTIPORT VIDEO RAM
IBM025160
IBM025161
IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 48 of 65
33G0307
SA14-4751-05
Revised 3/98
Early Write Cycle
An early Write cycle is executed by bringing W low before CE falls. Data is strobed by CE with setup and hold
times referenced to this signal. This is the mode that is generally used for graphics applications. TRG can be
in any state while W is active.
Late Write Cycle
A late Write is executed by bringing W low after CE goes low. The input data is strobed by W with setup and
hold times referenced to W signal. The late Write cycle is used for Read-Modify-Write operations.
Write-per-Bit Mask (WPBM) Cycle
A Write-Per-Bit Mask cycle uses an I/O mask function to allow the system designer the flexibility of writing or
not writing any combinations of DQ
0
through DQ
15
. Two types of masking are possible:
1. Non-persistent Mask or New mask
This mask has to be loaded at each RE fall time as shown in the timing diagram on page 34. W must be
low as RE falls. The DQs latched at RE fall time are used as mask bits for Write cycle(s) for the particular
RE cycle. If mask bit is “1”, the corresponding DQ input bit is written. If mask bit is “0”, the corresponding
DQ input is not written.
2. Persistent Mask or Old Mask
If a Load Mask Register cycle has been performed and has not been cleared by a CBR refresh cycle prior
to a Write cycle, and W is low at RE fall time, data at DQ pins at RE fall time will be ignored and the data
from Mask Register is applied to the following:
a. DQ inputs during Write cycles if W is low at RE fall time.
b. Color Register data during Block Write and Flash Write cycles if W is low at RE fall time.
Read-Write/Read-Modify-Write Cycle
A Read-Modify-Write is performed by first performing a normal Read, then tri-stating the DQ pins with TRG,
placing data to be written on the DQ pins, and then executing a Write operation. A WPBM can be loaded at
the falling edge of RE. The input data is strobed in reference to W. This operation is illustrated in the timing
diagram on page 24.
Load Mask Register Cycle
In this cycle, data on DQ pins is written to a 16-bit write mask register, where it is retained and used by sub-
sequent masked Write and masked Block Write cycles. This mask can be cleared by executing CBR cycle or
by turning the power off. The mask data in the Mask Register can be changed by issuing another Load Mask
Register cycle.
Load Color Register Cycle
The load color register cycle is used to load the 16 bit color register, where it is retained to be used for data
during Block Write and Flash Write operations.
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