參數(shù)資料
型號: IBM025161
廠商: IBM Microeletronics
英文描述: 4Mb(256K X 16) MULTIPORT VIDEO RAM(4M位(256K X 16)多端口視頻RAM)
中文描述: 4Mb的(256 × 16)多端口視頻內(nèi)存(4分位(256 × 16)多端口視頻內(nèi)存)
文件頁數(shù): 50/65頁
文件大小: 841K
代理商: IBM025161
IBM025170
IBM025171
256K X 16 MULTIPORT VIDEO RAM
IBM025160
IBM025161
IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 50 of 65
33G0307
SA14-4751-05
Revised 3/98
Flash Write
The Flash Write operation causes an entire row (512 x 16 bits) of data to be written with the contents of the
color register. The color register must be loaded on a previous Load Color Register (LCR) cycle. The Flash
Write operation can be without Mask, with new mask WPBM or old mask WPBM as explained in mask write
operations. The only difference is that the mask is applied for the data in the whole row.
Note that there is no
provision for individual byte control, therefore both the bytes will be written or masked
.
Fast Page Cycle Operation
Fast page mode cycles allow faster memory access by using the same row address while successive column
addresses are strobed onto the chip. The RE signal is kept low while successive CE cycles are executed.
The data rate is faster because row addresses are maintained internally and do not have to be reapplied. In
fast page mode operation, Read, Write, Read-modify-Write cycles may be executed. During a Fast-page
read cycle, the DQ pins stay in high-Z until valid data appears at the output pins at access time. The access
time in this cycle will be the longest of the following intervals.
t
ACP
t
CP
+ t
T
+ t
CAC
= Access time from start of column precharge
= Column precharge time + transition time
+ Access time from CE fall time
= CE high to column address delay + t
AA
Extended Data Out (EDO)
I
n extended data out mode, the primary port output drivers are not turned off by the rising edge of CE
.
As rising edge of CE does not turn off the data, the resulting longer data valid time allows speedup of the fast
page cycle time.
Fast page mode applications that try to run at minimum cycle times find that timing
skews and propagation delays make the data valid time so narrow that reliable sampling is impossi-
ble.
EDO solves this problem by providing longer data valid time. The device access time is the longest of the
following intervals:
t
ACP
t
AA
t
CAC
The detailed explanation of EDO and Fast Page is given in the Application Note, “EDO for Higher Bandwidth”.
Serial Port Operation
The Serial port is always in either Read or Write mode. To switch the Serial port from Read to Write or vice
versa, a Transfer operation of the appropriate type must be executed. A Read Transfer operation will put the
Serial port into Read mode if it is not already in Read mode. A Write Transfer will switch the Serial port into
Write mode if it is not already in Write mode.
To prevent storing of the current contents of the SAM when
first switching to Write mode, a Write transfer operation with the WPBM set to block all 16 bits should
be performed
. when SE is low, each serial clock will cause a Read/Write of the SAM location addressed by
the internal Serial port address counter. When SE is high, the Serial port is disabled for Read/Write, and the
SDQs are in high-Z state.
Note that Each SC clock causes the internal address counter to increment
independent of the state of SE
.
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