參數(shù)資料
型號: IBM025161
廠商: IBM Microeletronics
英文描述: 4Mb(256K X 16) MULTIPORT VIDEO RAM(4M位(256K X 16)多端口視頻RAM)
中文描述: 4Mb的(256 × 16)多端口視頻內(nèi)存(4分位(256 × 16)多端口視頻內(nèi)存)
文件頁數(shù): 54/65頁
文件大?。?/td> 841K
代理商: IBM025161
IBM025170
IBM025171
256K X 16 MULTIPORT VIDEO RAM
IBM025160
IBM025161
IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 54 of 65
33G0307
SA14-4751-05
Revised 3/98
Full Register Write Transfer (Normal) Mode
The Full Write Transfer operation is illustrated in the timing diagram on page 44. This operation will store the
contents of the SAM at the address specified by row address (RA
8
- RA
0
) and CA
8
.
CA
8
controls the transfer of data to the particular half of the row. If CA
8
at CE fall time is “0”, the data from
SAM is stored in the lower half of the row. If CA
8
at CE fall time is “1”, the upper half of the selected row is
loaded. CA
7
-CA
0
address supplied by the user at CE fall time in a transfer cycle is used to provide the start-
ing location for writing the data in the Serial port on the next SC clock following the transfer. During the Full
Write Transfer cycle, a WPBM can be loaded at RE fall time to mask the selected data bits at transfer time.
Generally, it is a good practice to mask all the data bits at the first Full Write Transfer cycle to prevent
transferring of old data left over from previous Read Transfer operations.
A Full Register Write Transfer from SAM to DRAM is shown in the timing diagram on page 54. The example
shows a transfer based on user supplied CA
8
equals “1”. The Serial port counter is set to the address CA
7
-
CA
0
specified by the user at CE fall time during the Full Register Write Transfer cycle. The next SC clock fol-
lowing the transfer will start writing data from this point in the SAM.
Full Register Write Transfer (Normal) Mode
Rows
Cols
Array
511
SAM
0
127
128
255
0
383
511
255
127
CA
7
=0 CA
8
=0
CA
7
=1 CA
8
=0
CA
7
=0 CA
8
=1
CA
7
=1 CA
8
=1
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