
IBM025170
IBM025171
256K X 16 MULTIPORT VIDEO RAM
IBM025160
IBM025161
IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 65
33G0307
SA14-4751-05
Revised 3/98
t
SU(SFR)
DSF setup time before RE low
0
—
0
—
0
—
ns
t
T
Transition time (rise and fall)
3
50
3
50
3
50
ns
t
TLH
TRG hold time after RE low
6
—
6
—
8
—
ns
t
TLS
TRG setup time before RE low
0
—
0
—
0
—
ns
t
WSR
Write setup time before RE low
0
—
0
—
0
—
ns
t
WCR
Write hold time after RE low
20
—
20
—
25
—
ns
Read, Write, Read-Modify-Write and Refresh. Cycles (Part 2 of 2)
(Common Parameters)
Symbol
Parameter
-6H
-60
-70
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
1. An initial pause of 100
μ
s is required after power up followed by 8 CE before RE refresh cycles for proper device operation
2. AC measurements assume t
T
= 5ns.
3. Operation within the t
RCD
(max) limit ensures that t
RAC
(max.) can be met. t
RCD
(max.) is specified as a reference point only: If t
RCD
is greater than the specified t
RCD
(max) limit, then access time is controlled by t
CAC
.
4. Operation within the t
RAD
(max) limit ensures that t
RAC
(max.) can be met. t
RAD
(max.) is specified as a reference point only: If t
RAD
is greater than the specified t
RAD
(max) limit, then access time is controlled by t
AA
.
5. t
RCD
and t
CAH
cannot be at minimum values simultaneously. t
RCD
+ t
CAH
≥
45ns (60ns t
RAC
product), t
RCD
+ t
CAH
≥
50ns (70ns
t
RAC
product).
6. t
RWL
and t
RP
cannot be at minimum values simultaneously. t
RW
L + t
RP
≥
60ns (60ns t
RAC
product), t
RWL
+ t
RP
≥
70ns (70ns t
RAC
product).
7. t
CWL
and t
RP
cannot be at minimum values simultaneously. t
CWL
+ t
RP
≥
60ns (60ns t
RAC
product), t
CWL
+ t
RP
≥
70ns (70ns t
RAC
product).
8. t
CRP
must be 15ns (60ns t
RAC
) or 17ns (70ns t
RAC
) if a write-per-bit mask is used on the following RE cycle due to the fact that t
OFF
must be met.
9. During Serial port write transfer t
RCD
(max) = 100ns.