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參數(shù)資料
| 型號： | IBM01644F5B |
| 廠商： | IBM Microeletronics |
| 英文描述： | 16M x 8 13/11 Stacked DRAM(16M x 8 棧式動態(tài)RAM（帶24條地址線，其中13條為行地址選通，11條為列地址選通）) |
| 中文描述： | 16米x 8 13/11堆疊DRAM（1,600 × 8棧式動態(tài)隨機存儲器（帶24條地址線，其中13條為行地址選通，11條為列地址選通）） |
| 文件頁數(shù)： | 6/26頁 |
| 文件大?。?/td> | 467K |
| 代理商： | IBM01644F5B |
IBM01644F5B
16M x 8 13/11 Stacked DRAM
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 6 of 26
96H5533
GA15-5143-00
Revised 03/97
AC Characteristics
(T
A
=0 to +70
°
C, V
CC
=3.3
±
0.3V)
1. An initial pause of 100
μ
s is required after power-up followed by 8 CAS before RAS refresh cycles before proper device operation is
achieved.
2. AC measurements assume t
T
=2ns.
3. V
IH
(min.) and V
IL
(max.) are reference levels for measuring timing of input signals. Also, transition times are measured between V
IH
and V
IL
.
4. Valid column addresses are only A0 through A10.
Read, Write, Read-Modify-Write and Refresh Cycle
(Common Parameters)
Symbol
Parameter
-50
-60
Units
Notes
Min.
Max.
Min.
Max.
t
RC
Random Read or Write Cycle Time
84
—
104
—
ns
t
RP
RAS Precharge Time
30
—
40
—
ns
t
CP
CAS Precharge Time
8
—
10
—
ns
t
RAS
RAS Pulse Width
50
100k
60
100k
ns
t
CAS
CAS Pulse Width
8
100k
10
100k
ns
t
ASR
Row Address Setup Time
0
—
0
—
ns
t
RAH
Row Address Hold Time
7
—
10
—
ns
t
ASC
Column Address Setup Time
0
—
0
—
ns
t
CAH
Column Address Hold Time
7
—
10
—
ns
t
RCD
RAS to CAS Delay Time
11
37
14
45
ns
1
t
RAD
RAS to Col. Address Delay Time
9
25
12
30
ns
2
t
RSH
RAS Hold Time
8
—
10
—
ns
t
CSH
CAS Hold Time
40
—
50
—
ns
t
CRP
CAS to RAS Precharge Time
5
—
5
—
ns
t
DZO
OE Delay Time From D
IN
0
—
0
—
ns
3
t
DZC
CAS Delay Time From D
IN
0
—
0
—
ns
3
t
T
Transition Time (Rise and Fall)
1
50
1
50
ns
4
1. Operation within the t
RCD
(max.) limit ensures that t
RAC
(max.) can be met. t
RCD
(max.) is specified as a reference point only. If
t
RCD
is greater than the specified t
RCD
(max.) limit, then access time is controlled by t
CAC
.
2. Operation within the t
RAD
(max.) limit ensures that t
RAC
(max.) can be met. t
RAD
(max.) is specified as a reference point only. If
t
RAD
is greater than the specified t
RAD
(max.) limit, then access time is controlled by t
AA
.
3. Either t
DZC
or t
DZO
must be satisfied.
4. AC measurements assume t
T
= 2ns.
Discontinued (8/98 - last order; 12/98 last ship)
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