參數(shù)資料
型號(hào)： HYB25D128400CT-5
廠(chǎng)商： QIMONDA AG
元件分類(lèi)： DRAM
英文描述： 32M X 4 DDR DRAM, 0.7 ns, PDSO66
封裝： PLASTIC, TSOP2-66
文件頁(yè)數(shù)： 29/44頁(yè)
文件大小： 2618K
代理商： HYB25D128400CT-5
HYB25D128[40/80/16]0C[C/E/F/T]
128-Mbit Double-Data-Rate SDRAM
Internet Data Sheet
Rev. 1.70, 2008-04
35
03292006-U5AN-6TI1
TABLE 25
I
DD Conditions
Parameter
Symbol
Operating Current: one bank; active/ precharge;
t
RC = tRCMIN; tCK = tCKMIN;
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two
clock cycles.
I
DD0
Operating Current: one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
I
DD1
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE
≤V
ILMAX; tCK = tCKMIN
I
DD2P
Precharge Floating Standby Current: CS
≥ V
IHMIN, all banks idle;
CKE
≥ V
IHMIN; tCK = tCKMIN, address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS
and DM.
I
DD2F
Precharge Quiet Standby Current: CS
≥ V
IHMIN, all banks idle; CKE ≥ VIHMIN; tCK = tCKMIN, address and other
control inputs stable at
≥ V
IHMIN or ≤ VILMAX; VIN=VREF for DQ, DQS and DM.
I
DD2Q
Active Power-Down Standby Current: one bank active; power-down mode;
CKE
≤ V
ILMAX; tCK= tCKMIN; VIN = VREF for DQ, DQS and DM.
I
DD3P
Active Standby Current: one bank active; CS
≥ V
IHMIN; CKE ≥ VIHMIN; tRC = tRASMAX; tCK = tCKMIN; DQ, DM and DQS
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle
I
DD3N
Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,
CL = 3 for DDR333;
t
CK = tCKMIN; IOUT =0mA
I
DD4R
Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing
once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A,
CL = 3 for DDR333;
t
CK = tCKMIN
I
DD4W
Auto-Refresh Current:
t
RC = tRFCMIN, burst refresh
I
DD5
Self-Refresh Current: CKE
≤ 0.2 V; external clock on; t
CK = tCKMIN
I
DD6
Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test
conditions.
I
DD7
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