參數(shù)資料
型號(hào)： HYB25D128400CT-5
廠商： QIMONDA AG
元件分類(lèi)： DRAM
英文描述： 32M X 4 DDR DRAM, 0.7 ns, PDSO66
封裝： PLASTIC, TSOP2-66
文件頁(yè)數(shù)： 28/44頁(yè)
文件大?。?/td> 2618K
代理商： HYB25D128400CT-5
HYB25D128[40/80/16]0C[C/E/F/T]
128-Mbit Double-Data-Rate SDRAM
Internet Data Sheet
Rev. 1.70, 2008-04
34
03292006-U5AN-6TI1
1) 0
°C ≤
T
A ≤ 70 °C; VDD = VDDQ = 2.5 V ± 0.2 V (DDR266A, DDR333B); VDD = VDDQ = +2.6 V ± 0.1 V (DDR400).
2) Input slew rate
≥ 1 V/ns.
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is
V
REF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT.
6) For each of the terms, if not already an integer, round to the next highest integer.
t
CK is equal to the actual system clock cycle time.
7)
t
HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate
≥ 1.0 V/ns , slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between
V
IH.AC and VIL.AC.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending
on
t
DQSS.
11) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
Active to Read or Write delay
t
RCD
20
—
ns
Average Periodic Refresh Interval
t
REFI
—
15.6
μs
Auto-refresh to Active/Auto-refresh command period
t
RFC
75
—
ns
Precharge command period
t
RP
20
—
ns
Read preamble
t
RPRE
0.9
1.0
t
CK
Read postamble
t
RPST
0.40
0.60
t
CK
Active bank A to Active bank B command
t
RRD
15
—
ns
Write preamble
t
WPRE
0.25
—
t
CK
Write preamble setup time
t
WPRES
0—
ns
Write postamble
t
WPST
0.40
0.60
t
CK
Write recovery time
t
WR
15
ns
Internal write to read command delay
t
WTR
1—
t
CK
Exit self-refresh to non-read command
t
XSNR
75
—
ns
Exit self-refresh to read command
t
XSRD
200
—
t
CK
Parameter
Symbol
–7
Unit Note/ Test
Condition 1)
DDR266A
Min.
Max.
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