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| 型號(hào)： | HYB25D128400CT-5 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 15/44頁 |
| 文件大?。?/td> | 2618K |
| 代理商： | HYB25D128400CT-5 |
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HYB25D128[40/80/16]0C[C/E/F/T]
128-Mbit Double-Data-Rate SDRAM
Internet Data Sheet
Rev. 1.70, 2008-04
22
03292006-U5AN-6TI1
TABLE 15
Truth Table 3: Clock Enable (CKE)
1. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n.
4. All states and sequences not shown are illegal or reserved.
Current State
CKE n-1
CKEn
Command n
Action n
Notes
Previous
Cycle
Current
Cycle
Self Refresh
L
X
Maintain Self-Refresh
1)
V
REF must be maintained during Self Refresh operation
Self Refresh
L
H
Deselect or NOP
Exit Self-Refresh
2)
2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (
t
XSNR) period. A minimum of 200
clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
Power Down
L
X
Maintain Power-Down
–
Power Down
L
H
Deselect or NOP
Exit Power-Down
–
All Banks Idle
H
L
Deselect or NOP
Precharge Power-Down Entry
–
All Banks Idle
H
L
AUTO REFRESH
Self Refresh Entry
–
Bank(s) Active
H
L
Deselect or NOP
Active Power-Down Entry
–
H
See Table 16
––
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|---|---|
| HYB25D128400CT-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128800AT-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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| HYB25D128800ATL-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
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