參數(shù)資料
型號(hào)： HYB25D128400CT-5
廠商： QIMONDA AG
元件分類： DRAM
英文描述： 32M X 4 DDR DRAM, 0.7 ns, PDSO66
封裝： PLASTIC, TSOP2-66
文件頁(yè)數(shù)： 22/44頁(yè)
文件大?。?/td> 2618K
代理商： HYB25D128400CT-5
HYB25D128[40/80/16]0C[C/E/F/T]
128-Mbit Double-Data-Rate SDRAM
Internet Data Sheet
Rev. 1.70, 2008-04
29
03292006-U5AN-6TI1
5.2
AC Characteristics
Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions,
I
DD Specifications and Conditions, and Electrical Characteristics and AC Timing.
Notes
1. All voltages referenced to
V
SS.
2. Tests for AC timing,
I
DD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Figure 5 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended
to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a
production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system
environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line
terminated at the tester electronics).
4. AC timing and
I
DD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced
to
V
REF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between
V
IL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as
a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above
(below) the DC input LOW (HIGH) level).
6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR SDRAM Slew
Rate Standards, Overshoot & Undershoot specification and Clamp
V-I characteristics see the latest Industry specification
for DDR components.
FIGURE 5
AC Output Load Circuit Diagram / Timing Reference Load
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