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| 型號(hào)： | HYB25D128400CT-5 |
| 廠商： | QIMONDA AG |
| 元件分類： | DRAM |
| 英文描述： | 32M X 4 DDR DRAM, 0.7 ns, PDSO66 |
| 封裝： | PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 16/44頁 |
| 文件大小： | 2618K |
| 代理商： | HYB25D128400CT-5 |
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HYB25D128[40/80/16]0C[C/E/F/T]
128-Mbit Double-Data-Rate SDRAM
Internet Data Sheet
Rev. 1.70, 2008-04
23
03292006-U5AN-6TI1
TABLE 16
Truth Table 4: Current State Bank n - Command to Bank n (same bank)
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 15 and after
t
XSNR/tXSRD has been met (if the previous state
was self refresh).
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed
to be issued to that bank when in that state. Exceptions are covered in the notes below.
3) Current state definitions: Idle: The bank has been precharged, and
t
RP has been met. Row Active: A row in the bank has been activated,
and
t
RCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with
Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge
disabled, and has not yet terminated or been terminated.
4) The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration of a Precharge
command and ends when
t
RP is met. Once tRP is met, the bank is in the idle state. Row Activating: Starts with registration of an Active
command and ends when
t
RCD is met. Once tRCD is met, the bank is in the “row active” state. Read w/Auto Precharge Enabled: Starts with
registration of a Read command with Auto Precharge enabled and ends when
t
RP has been met. Once tRP is met, the bank is in the idle
state. Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when
t
RP has
been met. Once
t
RP is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be
issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and
according to Table 17.
5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive
clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when
t
RFC is met. Once tRFC is
met, the DDR SDRAM is in the “all banks idle” state. Accessing Mode Register: Starts with registration of a Mode Register Set command
and ends when
t
MRD has been met. Once tMRD is met, the DDR SDRAM is in the “all banks idle” state. Precharging All: Starts with
registration of a Precharge All command and ends when
t
RP is met. Once tRP is met, all banks is in the idle state.
6) All states and sequences not shown are illegal or reserved.
7) Not bank-specific; requires that all banks are idle.
8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
9) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.
11) Requires appropriate DM masking.
Current State CS
RAS CAS WE Command
Action
Notes
Any
H
X
Deselect
NOP. Continue previous operation.
L
H
No Operation
NOP. Continue previous operation.
Idle
L
H
Active
Select and activate row
LL
LH
AUTO REFRESH
–
L
MODE REGISTER SET –
Row Active
L
H
L
H
Read
Select column and start Read burst
L
H
L
Write
Select column and start Write burst
L
H
L
Precharge
Deactivate row in bank(s)
Read (Auto
Precharge
Disabled)
L
H
L
H
Read
Select column and start new Read burst
L
H
L
Precharge
Truncate Read burst, start Precharge
L
H
L
BURST TERMINATE
Write (Auto
Precharge
Disabled)
L
H
L
H
Read
Select column and start Read burst
L
H
L
Write
Select column and start Write burst
L
H
L
Precharge
Truncate Write burst, start Precharge
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