參數(shù)資料
型號： HW-V5GBE-DK-UNI-G-PROMO2
廠商： Xilinx Inc
文件頁數(shù)： 84/91頁
文件大?。?/td> 0K
描述： KIT DEV V5 LXT GIGABIT ETHERNET
產(chǎn)品變化通告： Product Notice_Dev Systems Product
標準包裝： 1
系列： Virtex®
類型： 開發(fā)套件
適用于相關產(chǎn)品： XC5VLX50T
所含物品： 板和軟件
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
85
Revision History
The following table shows the revision history for this document.
Table 100: Sample Window
Symbol
Description
Device
Speed Grade
Units
-3
-2
-1
TSAMP
Sampling Error at Receiver Pins(1)
All
450
500
550
ps
TSAMP_BUFIO
Sampling Error at Receiver Pins using BUFIO(2)
All
350
400
450
ps
Notes:
1.
This parameter indicates the total sampling error of Virtex-5 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 DCM jitter
- DCM accuracy (phase offset)
- DCM phase shift resolution
These measurements do not include package or clock tree skew.
2.
This parameter indicates the total sampling error of Virtex-5 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.
Table 101: Source-Synchronous Pin-to-Pin Setup/Hold and Clock-to-Out
Symbol
Description
Speed Grade
Units
-3
-2
-1
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
TPSCS/TPHCS
Setup/Hold of I/O clock
–0.56
1.59
–0.54
1.72
–0.54
1.91
ns
Pin-to-Pin Clock-to-Out Using BUFIO
TICKOFCS
Clock-to-Out of I/O clock
4.42
4.82
5.40
ns
Date
Version
Revision
04/14/06
1.0
Initial Xilinx release.
05/12/06
1.1
First version posted to the Xilinx website. Minor typographical edits. Revised design software version on
Revised TIDELAYRESOLUTION in Table 64, page 44.
Revised TDSPCKO in Table 69, page 48.
05/24/06
1.2
Added register-to-register parameters to Table 52.
08/04/06
1.3
Added VDRINT, VDRI, and CIN values to Table 3.
Added HSTL_I_12 and LVCMOS12 to Table 7 and renumbered the notes.
Removed pin-to-pin performance (Table 12). Updated and added values to register-register
performance Table 52 (was Table 13).
Added values to Table 53.
Updated the speed specification version above Table 54.
Added to Table 56 the I/O standards: HSTL_II_T_DCI, HSTL_II_T_DCI_18, SSTL2_II_T_DCI, and
SSTL18_II_T_DCI.
Revised FMAX values in Table 68, and RDWR_B Setup/Hold values in Table 70.
In Table 74, changed FVCOMAX, removed TLOCKMIN, and revised TLOCKMAX values, also removed note
pointing to Architecture Wizard.
Removed Note 2 on Table 88.
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