參數(shù)資料
型號(hào)： HSP50214BVI
廠商： HARRIS SEMICONDUCTOR
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Programmable Downconverter
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP120
文件頁(yè)數(shù)： 54/60頁(yè)
文件大?。?/td> 573K
代理商： HSP50214BVI
3-54
11-10
Q Data Serial Output
Tag Bit
(See I Data Serial Output Tag selection above).
9-8
Magnitude Data Serial
Output Tag Bit
(See I Data Serial Output Tag selection above).
7-6
Phase Data Serial
Output Tag Bit
(See I Data Serial Output Tag selection above).
5-4
Frequency Data Serial
Output Tag Bit
(See I Data Serial Output Tag selection above).
3-2
AGC Data Serial Out-
put Tag Bit
(See I Data Serial Output Tag selection above).
1-0
Timing Error Data Se-
rial Output Tag Bit
(See I Data Serial Output Tag selection above).
CONTROL WORD 21: BUFFER RAM OUTPUT CONTROL REGISTER (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
FUNCTION
DESCRIPTION
31-16
Reserved
Reserved.
15
Output Buffer Mode
0- The output buffer operates in snapshot mode.
1- The output buffer operates in FIFO mode.
14-12
FIFO Mode Depth
Threshold
In FIFO mode, when the FIFO depth reaches this threshold, an interrupt is generated and the READY
flag is asserted. The threshold may be set from 0 to 7. Bit 14 is the MSB. The interrupt is generated when
the FIFO depth reaches the threshold, as the FIFO fills.
11-4
Snapshot Mode
Interval
In snapshot mode, the interval between snapshots in the output sample times is determined by this 8-
bit binary number, i.e. 256, (2
8
), sample time counts between snapshot samples. Program this parame-
ter to 1 less than the desired interval. Bit 11 is the MSB.
3-0
Snapshot Mode
Number of Samples
In snapshot mode, the number of samples stored each time the snapshot interval counter times out is
equal to the decimal version of this 4-bit number. The range is 1- 8. Bit 3 is the MSB.
CONTROL WORD 22: BUFFER RAM OUTPUT FIFO RESET (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
FUNCTION
DESCRIPTION
N/A
FIFO reset
A write to this address increments the output FIFO RAM address pointers to READ = 111 and WRITE
= 000.
CONTROL WORD 23: INCREMENT OUTPUT FIFO (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
FUNCTION
DESCRIPTION
N/A
FIFO Strobe
A write to this address increments the output FIFO/buffer to the next sample set.
CONTROL WORD 24: SYNCOUT STROBE OUTPUT PIN
(SYNCHRONIZED TO CLKIN OR PROCCLK DEPENDING ON PROGRAMMING IN CONTROL WORD 0)
BIT
POSITION
FUNCTION
DESCRIPTION
N/A
SYNCOUT Strobe
A write to this address generates a one clock period wide strobe on the SYNCOUT pin that is synchro-
nized to the clock. This strobe may be synchronized to CLKIN or PROCCLK based on the programming
of bit 3 of Control Word 0.
CONTROL WORD 20: BUFFER RAM, DIRECT PARALLEL, AND DIRECT SERIAL OUTPUT CONFIGURATION
(SYNCHRONIZED WITH PROCCLK) (CONTINUED)
BIT
POSITION
FUNCTION
DESCRIPTION
HSP50214B
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