參數(shù)資料
型號(hào)： HSP50214BVI
廠商： HARRIS SEMICONDUCTOR
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Programmable Downconverter
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP120
文件頁(yè)數(shù)： 37/60頁(yè)
文件大?。?/td> 573K
代理商： HSP50214BVI
3-37
The serial direct output can be programmed to output less
than 16 bits. New output data preempts old output data, so if
SERSYNC is programmed to precede the MSB, then data
will shift out until new data comes along. Note that if
SERSYNC is programmed to follow the LSB, then a sync will
never occur.
Buffer RAM Output Port
The Buffer RAM parallel output mode utilizes a RAM to store
output data for future retrieval by either the 8-bit
microprocessor that is configuring the PDC or by a 16-bit
baseband processing engine (which could also be a
microprocessor). Data is output from the RAM only on request
and can be obtained from either the 8-bit
μ
P interface or from
a 16-bit interface that uses the two LSBytes of AOUT and
BOUT. The RAM holds up to eight 80-bit sample sets. Each
sample set includes 16 bits of each I, Q, magnitude, phase,
and frequency data. The RAM samples are mapped as shown
in Table 16. The Buffer RAM controller supports both FIFO
and Snapshot modes.
FIGURE 35. EXAMPLE 2 SERIAL OUTPUT DATA STREAM
FIGURE 36. VALID SERSYNC CONFIGURATION OPTIONS
SEROUTA
THE REMAINING CHOICES FOR THE THIRD LINK ON SEROUTB ARE:
PHASE, FREQUENCY, AGC LEVEL, AND TIMING ERROR
CONTROL WORD 19, BITS 24-21 = 011
(3 DATA WORDS IN EACH SERIAL OUTPUT)
NOTE: Once magnitude is identified to follow Q,
it must be that way on both serial outputs.
DATA WORD 1
DATA WORD 2
DATA WORD 3
I
Q
MAGNITUDE
SEROUTB
DATA WORD 1
DATA WORD 2
DATA WORD 3
Q
MAGNITUDE
TBD
15
14
DATA SHIFT MSB FIRST
MSB WORD3
EARLY
SERSYNC
MODE
“NORMAL”
“INVERTED”
0
1
2
LATE
SERSYNC
MODE
“NORMAL”
“INVERTED”
MSB WORD2
1
15
14
1
2
2
15
14
MSB WORD1
1
2
LSB WORD2
LSB WORD1
2
0
1
2
2
3
2
3
SERSYNC PRECEDES MSB
SERSYNC FOLLOWS LSB
0
0
0
1
1
LSB WORD0
TABLE 16. RAM DATA STORAGE MAP
RAM
SAMPLE
SET
I
DATA
(000)
Q
DATA
(001)
|r|
DATA
(010)
Φ
DATA
(011)
F
DATA
(100)
0
I
0
(15:0)
Q
0
(15:0)
|r|
0
(15:0)
φ
0
(15:0)
f
0
(15:0)
1
I
1
(15:0)
Q
1
(15:0)
|r|
1
(15:0)
φ
1
(15:0)
f
1
(15:0)
2
I
2
(15:0)
Q
2
(15:0)
|r|
2
(15:0)
φ
2
(15:0)
f
2
(15:0)
3
I
3
(15:0)
Q
3
(15:0)
|r|
3
(15:0)
φ
3
(15:0)
f
3
(15:0)
4
I
4
(15:0)
Q
4
(15:0)
|r|
4
(15:0)
φ
4
(15:0)
f
4
(15:0)
5
I
5
(15:0)
Q
5
(15:0)
|r|
5
(15:0)
φ
5
(15:0)
f
5
(15:0)
6
I
6
(15:0)
Q
6
(15:0)
|r|
6
(15:0)
φ
6
(15:0)
f
6
(15:0)
7
I
7
(15:0)
Q
7
(15:0)
|r|
7
(15:0)
φ
7
(15:0)
f
7
(15:0)
NOTE: I and Q are sample aligned in time. |r| and
φ
are sample
aligned in time, but one sample delayed from I or Q. The
frequency sample is delayed in time from I or Q by 1
sample time + 63 tap FIR impulse response. If the FIR is
set to decimate, the FIR output will be repeated every
sample time until a new value appears at the filter output.
(i.e., the frequency samples are clocked out at the I, Q
sample rate regardless of decimation.)
HSP50214B
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