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參數(shù)資料
| 型號(hào)： | HSP50214BVI |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Programmable Downconverter |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP120 |
| 文件頁數(shù)： | 16/60頁 |
| 文件大小： | 573K |
| 代理商： | HSP50214BVI |
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3-16
NOTE: COF loading and timing is relative to CLKIN while SOF
loading and timing is relative to PROCCLK.
NOTE: T
D
can be 0, and the fastest rate is with 8-bit word width.
The assertion of the COFSYNC (or SOFSYNC) starts a count
down from the programmed word width. On following CLKs,
data is shifted into the register until the specified number of
bits have been input. At this point the contents of the register
are transferred from the Shift Register to the respective 32-bit
Holding Register. The Shift Register can accept new data on
the following CLK. If the serial input word is defined to be less
than 32 bits, it will be transferred to the MSBs of the 32-bit
Holding Register and the LSBs of the Holding Register will be
zeroed. See Figure 14 for details.
CIC Decimation Filter
The mixer output may be filtered with the CIC filter or it may be
routed directly to the halfband filters. The CIC filter is used to
reduce the sample rate of a wideband signal to a rate that the
halfbands and programmable filters can process, given the
maximum computation speed of PROCCLK. (See Halfband
and FIR Filter Sections for techniques to calculate this value).
Prior to the CIC filter, the output of the mixer goes through a
barrel shifter. The shifter is used to adjust the gain in 6dB
steps to compensate for the variation in CIC filter gain with
decimation. (See Equation 6). Fine gain adjustments must
be done in the AGC Section. The shifter is controlled by the
sum of a 4-bit CIC Shift Gain word from the microprocessor
and a 3-bit gain word from the GAINADJ(2:0) pins. The three
bit value is pipelined to match the delay of the input samples.
The sum of the 3 and 4-bit shift gain words saturates at a
value of 15. Table 1 details the permissible values for the
GAINADJ(2:0) barrel shifter control, while Figure 15 shows
the permissible CIC Shift Gain values.
The CIC filter structure for the HSP50214B is fifth order; that
is it has five integrator/comb pairs. A fifth order CIC has
84dB of alias attenuation for output frequencies below 1/8
the CIC output sample rate.
The decimation factor of the CIC filter is programmed in
Control Word 0, Bits 12 - 7. The CIC Shift Gain is
programmed in Control Word 0, Bits 16-13. The CIC Bypass
is set in Control Word 0, Bit 6. When bypassing the CIC filter,
the ENI signal must be de-asserted between samples, i.e.,
the CLKIN rate must be
≥
2
f
S
.
CIC Gain Calculations
The gain through the CIC filter increases with increased
decimation. The programmable barrel shifter that precedes
the first integrator in the CIC is used to offset this variation.
Gain variations due to decimation should be offset using the
4-bit CIC Shift Gain word. This allows the input signal level to
be adjusted in 6dB steps to control the CIC output level.
The gain at each stage of the CIC is:
R
N
,
=
where R is the decimation factor and N is the number of stages.
The input to the CIC from the mixer is 15 bits, and the bit widths
of the accumulators for the five stages in the HSP50214B are
40, 36, 32, 32, and 32, as shown in Figure 16. This limits the
maximum decimation in the CIC to 32 for a full scale input.
IfRis32,thegainthroughallfiveintegratorstagesis32
5
=2
25
.
(The gain through the last four CIC stages is 2
20
, through the
last 3 it is 2
15
, etc.). The sum of the input bits and the growth
bits cannot exceed the accumulator size. This means that for a
decimation of 32 and 15 input bits, the first accumulator must
be 15 + 25 = 40 bits.
Thus, the value of the CIC Shift Gain word can be
calculated:
NOTE: The number of input bits is IIN. (If the number of bits into
the CIC filter is used, the value 40 replaces 39).
For 14 bits, Equation 7 becomes:
FIGURE 15. CIC SHIFT GAIN VALUES
15
13
12
11
10
9
8
7
6
5
3
2
1
0
16
4
40
32
24
64
56
48
DECIMATION (R)
C14
8
12
20
28
36
44
52
60
8-BIT INPUT
10-BIT INPUT
12-BIT INPUT
14-BIT INPUT
ALLOWABLE CIC SHIFT
GAINS ARE BELOW THE
CURVES
TABLE 3. GAIN ADJUST CONTROL AND CIC DECIMATION
GAIN VALUE
(dB)
GAIN ADJ(2:0)
MAX. CIC
DECIMATION
0
000
32
6
001
27
12
010
24
18
011
21
24
100
18
30
101
16
36
110
12
42
111
10
k
(EQ. 6)
(EQ. 7)
SG = FLOOR 39 -
IIN
(
)
- log
2
(R)
5
for 4<R<32
for R = 4
= 15
SG
FLOOR 25
log
2
R
( )
5
]
for 4
R
32
<
<
4
–
=
15
=
for R
=
(EQ. 8A)
HSP50214B
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP50214BVIZ | 功能描述:上下轉(zhuǎn)換器 120L MQFP INDTEMP 14-BIT PROG DWNCNVRT RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| HSP50214VC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50214VI | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP50215 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
| HSP50215EVAL | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:DSP Modulator Evaluation Board |
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