參數(shù)資料
型號(hào)： HSP50214BVI
廠商： HARRIS SEMICONDUCTOR
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Programmable Downconverter
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP120
文件頁(yè)數(shù)： 33/60頁(yè)
文件大?。?/td> 573K
代理商： HSP50214BVI
3-33
Data Ready Signal Assertion Rate:
The assertion rate of the DATARDY signal Is the data
transition rate of the A
OUT
output data either [I, |r| or f]. The
time alignment of parallel data words available for output are
as follows:
I and Q are aligned in time,
|r| and are time aligned, but one sample clock delayed
from the associated I and Q samples.
DATARDY Is asserted time aligned with and at the same
rate as the data type selected for the AOUT output.
Figure 31 details the timing of the AOUT and DATARDY for
an AOUT = I data selection.
Note that the BOUT data word may be at a different rate and
skewed in time with respect to DATARDY, depending on the
type of data selected for output. This is because of the timing
relationships defined above, and because the DATARDY is
driven by the AOUT signal. Figure 32 details such a
configuration.
When the f (frequency) word is selected for output on AOUT,
the DATARDY signal is asserted at the discriminator FIR filter
output rate, which will be a reduced rate when decimation is
engaged in the filter. The f (frequency)S output is delayed
from the associated I and Q samples one sample time plus,
the discriminator FIR filter impulse response time. Figure 33
details the timing of this configuration for a FIR filter that
decimates by 4.
NOTE: ThenumberofPROCCLKSperoutput symbolisnot representative,butshowntobesmallforclarity ofestablishingtimingwithrespect
to the DATARDY signal. For each application, the relationship of the output symbol rate to PROCCLK must be properly illustrated to determine
the exact nature of the timing.
FIGURE 31. DATARDY WAVEFORMS WHEN I (READ DATA) IS SELECTED AS AOUT
FIGURE 32. DATARDY WAVEFORMS WHEN |r| (MAGNITUDE) IS SELECTED AS AOUT
NOTE: I and Q are sample aligned in time. |r| and
φ
are sample aligned in time, but one sample delayed from I or Q. The frequency
sampleisdelayedintimefromIorQby1sampletime+63tapFIRimpulseresponse.IftheFIRissettodecimateandfrequency
is selected for AOUT, the DATARDY signal will be at the discriminator FIR output (decimated) rate.
FIGURE 33. DATARDY WAVEFORMS WHEN f (FREQUENCY) IS SELECTED AS AOUT
AOUT
PROCCLK
DATARDY
I0
I1
I2
I3
I4
I5
I6
DR0
DR1
DR2
DR3
DR4
DR5
DR6
AOUT
PROCCLK
DATARDY
|r|0
|r|1
|r|2
|r|3
|r|4
|r|5
|r|6
DR0
DR1
DR2
DR3
DR4
DR5
DR6
BOUT
Q0
Q1
Q2
Q3
Q4
Q5
Q6
AOUT
PROCCLK
DATARDY
f0 (R = 4)
DR0
BOUT
Q0
Q1
Q2
Q3
Q4
Qn
Qn+1
Qn+2
1 + FIR Delay
DR-1
HSP50214B
相關(guān)PDF資料
PDF描述
HT84 ADSL Coupling Transformers
HT84-00594 ADSL Coupling Transformers
HT8400594S ADSL Coupling Transformers
HT84-00595 ADSL Coupling Transformers
HT84-00596 ADSL Coupling Transformers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HSP50214BVIZ 功能描述:上下轉(zhuǎn)換器 120L MQFP INDTEMP 14-BIT PROG DWNCNVRT RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128
HSP50214VC 制造商:Rochester Electronics LLC 功能描述:- Bulk
HSP50214VI 制造商:Rochester Electronics LLC 功能描述:- Bulk
HSP50215 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:DSP Modulator Evaluation Board
HSP50215EVAL 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:DSP Modulator Evaluation Board
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*