參數(shù)資料
型號(hào)： HSP50214BVI
廠商： HARRIS SEMICONDUCTOR
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Programmable Downconverter
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP120
文件頁(yè)數(shù)： 51/60頁(yè)
文件大?。?/td> 573K
代理商： HSP50214BVI
3-51
CONTROL WORD 13: TIMING PHASE OFFSET (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
FUNCTION
DESCRIPTION
31-8
Reserved
Reserved.
7-0
Timing NCO Phase
Offset
These bits are used to offset the phase of the Timing NCO. The range is 0 to 1 times the resampler input
period interpreted either as
±
T/2(2’s complement) or 0 to T (offset binary). Bit 7 is the MSB. This location
is a holding register. After loading, a transfer to the Active Register is done by writing to Control Word 15
or by generating a SYNCIN2 with Control Word 11, Bit 5 set to 1.
CONTROL WORD 14: TIMING FREQUENCY STROBE (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
FUNCTION
DESCRIPTION
N/A
Timing Frequency
Strobe
WritingtothisaddressupdatestheactivetimingNCOFrequencyRegisterinthetimingNCO(seeTiming
NCO Section).
CONTROL WORD 15: TIMING PHASE STROBE (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
FUNCTION
DESCRIPTION
N/A
Timing Phase Strobe
Writing to this address updates the active timing NCO Phase Offset Register in the timing NCO (see Tim-
ing NCO Section).
CONTROL WORD 16: RESAMPLING FILTER CONTROL (SYNCHRONIZED TO PROCCLK)
BIT
POSITION
FUNCTION
DESCRIPTION
31-12
Reserved
Reserved.
11-4
Re-Sampler Output
Pulse Delay
NOTE: These bits program the delay between output samples when interpolating. The extra outputs can
be delayed from 2 to 255 clocks from the first output. A delay of 2 equals 255 clocks of delay. A
delay of 0 or 1 is an invalid mode. When interpolating by 2, one extra output is generated; when
interpolating by 4, 3 extra outputs are generated. Program by the equation (PROCCLK/f
OUT
) - 1.
Bit 11 is the MSB.
NOTE: If less than 5 is programmed, there will not be sufficient time to fully update the output
buffer. If less than 16 is programmed, the serial output may be preempted. This means that
it won’t finish and if the sync is programmed to follow the data, there may never be a sync.
3
Re-Sampler Bypass
0- Resampling Filter Enabled. A valid combination of bits 2-0 must also be selected.
1- Resampling Filter Section (including Interpolation halfband filters) is bypassed.
2-0
Filter Mode Select;
2- HB2 Enabled
1- HB1 Enabled
0- Re-Sampler
Enabled
000- Not Valid.
001- Re-Sampler Enabled.
010- Halfband 1 Enabled.
011- Re-Sampler and Halfband Filter 1 Enabled.
100- Not Valid.
101- Not Valid.
110- Both Halfband Filters Enabled.
111- Re-Sampler and Both Halfband Filters Enabled.
HSP50214B
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